diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedBroadwell.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index dff32daa537..971a50196e4 100644 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -1229,7 +1229,7 @@ def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { let NumMicroOps = 5; let ResourceCycles = [1,1,3]; } -def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>; +def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { let Latency = 9; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 429558ef2c5..06a32fb0b1c 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -720,7 +720,7 @@ def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { let NumMicroOps = 17; let ResourceCycles = [1, 16]; } -def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>; +def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; //=== Floating Point x87 Instructions ===// //-- Move instructions --// diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 23113e0f0df..a866f843106 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -790,7 +790,7 @@ def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>; def : InstRW<[WriteMicrocoded], (instrs RDPMC)>; // RDRAND. -def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>; +def : InstRW<[WriteMicrocoded], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; // XGETBV. def : InstRW<[WriteMicrocoded], (instrs XGETBV)>; |
