diff options
6 files changed, 68 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index 768fba3f2fa..a5406ae11c7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -26,6 +26,10 @@ def gi_vop3mods : GIComplexOperandMatcher<s32, "selectVOP3Mods">, GIComplexPatternEquiv<VOP3Mods>; +def gi_vop3omods : + GIComplexOperandMatcher<s32, "selectVOP3OMods">, + GIComplexPatternEquiv<VOP3OMods>; + class GISelSop2Pat < SDPatternOperator node, Instruction inst, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index dde8fdccb73..f98f57ea047 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -537,6 +537,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, switch (I.getOpcode()) { default: break; + case TargetOpcode::G_SITOFP: case TargetOpcode::G_FMUL: case TargetOpcode::G_FADD: case TargetOpcode::G_FPTOUI: @@ -582,6 +583,14 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod }}; } +InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const { + return {{ + [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod + }}; +} InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index afe142c23a0..8283ab51741 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -78,6 +78,8 @@ private: InstructionSelector::ComplexRendererFns selectVOP3Mods0(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns + selectVOP3OMods(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns selectVOP3Mods(MachineOperand &Root) const; const SIInstrInfo &TII; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 996cef1110d..c4298331cf2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -91,6 +91,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST, setAction({G_FPTOSI, S32}, Legal); setAction({G_FPTOSI, 1, S32}, Legal); + setAction({G_SITOFP, S32}, Legal); + setAction({G_SITOFP, 1, S32}, Legal); + setAction({G_FPTOUI, S32}, Legal); setAction({G_FPTOUI, 1, S32}, Legal); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir new file mode 100644 index 00000000000..42fc095985a --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir @@ -0,0 +1,36 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @sitofp(i32 addrspace(1)* %global0) {ret void} +... +--- + +name: sitofp +legalized: true +regBankSelected: true + +# GCN-LABEL: name: sitofp +body: | + bb.0: + liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4 + + ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + %0:sgpr(s32) = COPY $sgpr0 + + ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr0 + + %2:vgpr(s64) = COPY $vgpr3_vgpr4 + + ; sitofp s + ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0 + %3:vgpr(s32) = G_SITOFP %0 + + ; sitofp v + ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0 + %4:vgpr(s32) = G_SITOFP %1 + + G_STORE %3, %2 :: (store 4 into %ir.global0) + G_STORE %4, %2 :: (store 4 into %ir.global0) +... +--- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir new file mode 100644 index 00000000000..649f8903cd1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir @@ -0,0 +1,14 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- +name: test_sitofp_f32_to_i32 +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: test_sitofp_f32_to_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_SITOFP %0 +... |
