diff options
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll | 19 |
2 files changed, 23 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index 2db7449d6aa..86ddb0722a1 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -6868,10 +6868,12 @@ multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm, def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?}, FPR64, FPR64, vecshiftL64, asm, - [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), - (i32 vecshiftL64:$imm)))]> { + [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> { let Inst{21-16} = imm{5-0}; } + + def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))), + (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>; } multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> { diff --git a/llvm/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll b/llvm/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll new file mode 100644 index 00000000000..a4c9cd8f106 --- /dev/null +++ b/llvm/test/CodeGen/ARM64/2014-04-28-sqshl-uqshl-i64Contant.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s + +; Check if sqshl/uqshl with constant shift amout can be selected. +define i64 @test_vqshld_s64_i(i64 %a) { +; CHECK-LABEL: test_vqshld_s64_i: +; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36 + %1 = tail call i64 @llvm.arm64.neon.sqshl.i64(i64 %a, i64 36) + ret i64 %1 +} + +define i64 @test_vqshld_u64_i(i64 %a) { +; CHECK-LABEL: test_vqshld_u64_i: +; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36 + %1 = tail call i64 @llvm.arm64.neon.uqshl.i64(i64 %a, i64 36) + ret i64 %1 +} + +declare i64 @llvm.arm64.neon.uqshl.i64(i64, i64) +declare i64 @llvm.arm64.neon.sqshl.i64(i64, i64) |
