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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPU.td33
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUGISel.td2
-rw-r--r--llvm/lib/Target/AMDGPU/BUFInstructions.td26
-rw-r--r--llvm/lib/Target/AMDGPU/DSInstructions.td14
-rw-r--r--llvm/lib/Target/AMDGPU/FLATInstructions.td8
-rw-r--r--llvm/lib/Target/AMDGPU/MIMGInstructions.td4
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.td16
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstructions.td4
-rw-r--r--llvm/lib/Target/AMDGPU/SMInstructions.td28
-rw-r--r--llvm/lib/Target/AMDGPU/SOPInstructions.td24
-rw-r--r--llvm/lib/Target/AMDGPU/VOP1Instructions.td28
-rw-r--r--llvm/lib/Target/AMDGPU/VOP2Instructions.td22
-rw-r--r--llvm/lib/Target/AMDGPU/VOP3Instructions.td54
-rw-r--r--llvm/lib/Target/AMDGPU/VOPCInstructions.td12
14 files changed, 138 insertions, 137 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 588d9766001..159be2070ac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -657,30 +657,23 @@ def NullALU : InstrItinClass;
// Predicate helper class
//===----------------------------------------------------------------------===//
-def isGFX6GFX7 :
- Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
- "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
- AssemblerPredicate<"!FeatureGCN3Encoding">;
+def isSICI : Predicate<
+ "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
+ "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
+>, AssemblerPredicate<"!FeatureGCN3Encoding">;
-def isGFX7Plus :
- Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
- AssemblerPredicate<"FeatureCIInsts">;
-
-def isGFX8Plus :
- Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
- AssemblerPredicate<"FeatureVIInsts">;
+def isVI : Predicate <
+ "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
+ AssemblerPredicate<"FeatureGCN3Encoding">;
-def isGFX9Plus :
- Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
+def isGFX9 : Predicate <
+ "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
AssemblerPredicate<"FeatureGFX9Insts">;
-def isGFX7 :
- Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
- AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">;
-
-def isGFX8 :
- Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">,
- AssemblerPredicate<"FeatureGCN3Encoding,FeatureVIInsts,!FeatureGFX9Insts">;
+// TODO: Either the name to be changed or we simply use IsCI!
+def isCIVI : Predicate <
+ "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
+ AssemblerPredicate<"FeatureCIInsts">;
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
AssemblerPredicate<"FeatureFlatAddressSpace">;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 6f725d60907..8049ebf02cb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -130,7 +130,7 @@ def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
let AddedComplexity = 100 in {
-let SubtargetPredicate = isGFX6GFX7 in {
+let SubtargetPredicate = isSICI in {
def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
}
def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 4164925484b..6acd7eb44bd 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -830,7 +830,7 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
// This is not described in AMD documentation,
// but 'lds' versions of these opcodes are available
// in at least GFX8+ chips. See Bug 37653.
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <
"buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1
>;
@@ -939,7 +939,7 @@ defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Pseudo_Atomics <
"buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
>;
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">;
}
@@ -1040,7 +1040,7 @@ let SubtargetPredicate = HasPackedD16VMem, D16Buf = 1 in {
defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_64>;
} // End HasPackedD16VMem.
-let SubtargetPredicate = isGFX7Plus in {
+let SubtargetPredicate = isCIVI in {
//===----------------------------------------------------------------------===//
// Instruction definitions for CI and newer.
@@ -1052,7 +1052,7 @@ let SubtargetPredicate = isGFX7Plus in {
def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
int_amdgcn_buffer_wbinvl1_vol>;
-} // End let SubtargetPredicate = isGFX7Plus
+} // End let SubtargetPredicate = isCIVI
//===----------------------------------------------------------------------===//
// MUBUF Patterns
@@ -1319,7 +1319,7 @@ multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Ins
>;
}
-let SubtargetPredicate = isGFX6GFX7 in {
+let SubtargetPredicate = isSICI in {
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
@@ -1327,7 +1327,7 @@ def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_con
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
-} // End SubtargetPredicate = isGFX6GFX7
+} // End SubtargetPredicate = isSICI
multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
PatFrag ld> {
@@ -1457,10 +1457,10 @@ multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo In
(Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0)
>;
}
-let SubtargetPredicate = isGFX6GFX7 in {
+let SubtargetPredicate = isSICI in {
defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, store_atomic_global>;
defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, store_atomic_global>;
-} // End Predicates = isGFX6GFX7
+} // End Predicates = isSICI
multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
@@ -1644,7 +1644,7 @@ class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real<op, ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
- let AssemblerPredicate=isGFX6GFX7;
+ let AssemblerPredicate=isSICI;
let DecoderNamespace="SICI";
let Inst{11-0} = !if(ps.has_offset, offset, ?);
@@ -1771,7 +1771,7 @@ class MTBUF_Real_si <bits<3> op, MTBUF_Pseudo ps> :
MTBUF_Real<ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> {
- let AssemblerPredicate=isGFX6GFX7;
+ let AssemblerPredicate=isSICI;
let DecoderNamespace="SICI";
let Inst{11-0} = !if(ps.has_offset, offset, ?);
@@ -1815,7 +1815,7 @@ defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_si <7>;
class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real_si<op, ps> {
- let AssemblerPredicate=isGFX7;
+ let AssemblerPredicate=isCIOnly;
let DecoderNamespace="CI";
}
@@ -1830,7 +1830,7 @@ class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> :
MUBUF_Real<op, ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
- let AssemblerPredicate=isGFX8Plus;
+ let AssemblerPredicate=isVI;
let DecoderNamespace="VI";
let Inst{11-0} = !if(ps.has_offset, offset, ?);
@@ -2005,7 +2005,7 @@ class MTBUF_Real_vi <bits<4> op, MTBUF_Pseudo ps> :
MTBUF_Real<ps>,
Enc64,
SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI> {
- let AssemblerPredicate=isGFX8Plus;
+ let AssemblerPredicate=isVI;
let DecoderNamespace="VI";
let Inst{11-0} = !if(ps.has_offset, offset, ?);
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index c359a318550..c099a29d1c8 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -547,7 +547,7 @@ def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
// Instruction definitions for CI and newer.
//===----------------------------------------------------------------------===//
-let SubtargetPredicate = isGFX7Plus in {
+let SubtargetPredicate = isCIVI in {
defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
@@ -566,13 +566,13 @@ defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
def DS_NOP : DS_VOID<"ds_nop">;
-} // let SubtargetPredicate = isGFX7Plus
+} // let SubtargetPredicate = isCIVI
//===----------------------------------------------------------------------===//
// Instruction definitions for VI and newer.
//===----------------------------------------------------------------------===//
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
let Uses = [EXEC] in {
def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
@@ -583,7 +583,7 @@ def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
-} // let SubtargetPredicate = isGFX8Plus
+} // let SubtargetPredicate = isVI
//===----------------------------------------------------------------------===//
// DS Patterns
@@ -727,7 +727,7 @@ class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, PatFrag frag> : GCNPat<
// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
// related to bounds checking.
-let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
+let OtherPredicates = [LDSRequiresM0Init, isCIVI] in {
def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, load_local_m0>;
def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, store_local_m0>;
}
@@ -830,7 +830,7 @@ def : Pat <
class DS_Real_si <bits<8> op, DS_Pseudo ds> :
DS_Real <ds>,
SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
- let AssemblerPredicates=[isGFX6GFX7];
+ let AssemblerPredicates=[isSICI];
let DecoderNamespace="SICI";
// encoding
@@ -1001,7 +1001,7 @@ def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
DS_Real <ds>,
SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
- let AssemblerPredicates = [isGFX8Plus];
+ let AssemblerPredicates = [isVI];
let DecoderNamespace="VI";
// encoding
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index fec3eb68a26..2179b21e0a6 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -490,7 +490,7 @@ defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
VReg_64, i64, atomic_dec_flat>;
-let SubtargetPredicate = isGFX7Plus in { // CI Only flat instructions : FIXME Only?
+let SubtargetPredicate = isCI in { // CI Only flat instructions : FIXME Only?
defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
VGPR_32, f32, null_frag, v2f32, VReg_64>;
@@ -510,7 +510,7 @@ defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
VReg_64, f64>;
-} // End SubtargetPredicate = isGFX7Plus
+} // End SubtargetPredicate = isCI
let SubtargetPredicate = HasFlatGlobalInsts in {
defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
@@ -916,7 +916,7 @@ def : FlatSignedAtomicPat <GLOBAL_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
FLAT_Real <op, ps>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
- let AssemblerPredicate = isGFX7;
+ let AssemblerPredicate = isCIOnly;
let DecoderNamespace="CI";
}
@@ -984,7 +984,7 @@ defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2
class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
FLAT_Real <op, ps>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
- let AssemblerPredicate = isGFX8Plus;
+ let AssemblerPredicate = isVI;
let DecoderNamespace="VI";
}
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 98d64403a2e..4071adcf200 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -263,14 +263,14 @@ multiclass MIMG_Atomic_Helper_m <mimg op, string asm, RegisterClass data_rc,
def _si : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "SICI", enableDasm>,
SIMCInstr<NAME, SIEncodingFamily.SI>,
MIMGe<op.SI> {
- let AssemblerPredicates = [isGFX6GFX7];
+ let AssemblerPredicates = [isSICI];
let DisableDecoder = DisableSIDecoder;
}
def _vi : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "VI", enableDasm>,
SIMCInstr<NAME, SIEncodingFamily.VI>,
MIMGe<op.VI> {
- let AssemblerPredicates = [isGFX8Plus];
+ let AssemblerPredicates = [isVI];
let DisableDecoder = DisableVIDecoder;
let MIMGEncoding = MIMGEncGfx8;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 1cf64ea809c..8438fc016be 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -5,12 +5,20 @@
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
+def isCI : Predicate<"Subtarget->getGeneration() "
+ ">= AMDGPUSubtarget::SEA_ISLANDS">;
+def isCIOnly : Predicate<"Subtarget->getGeneration() =="
+ "AMDGPUSubtarget::SEA_ISLANDS">,
+ AssemblerPredicate <"FeatureSeaIslands">;
+def isVIOnly : Predicate<"Subtarget->getGeneration() =="
+ "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
+ AssemblerPredicate <"FeatureVolcanicIslands">;
def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
class GCNPredicateControl : PredicateControl {
- Predicate SIAssemblerPredicate = isGFX6GFX7;
- Predicate VIAssemblerPredicate = isGFX8Plus;
+ Predicate SIAssemblerPredicate = isSICI;
+ Predicate VIAssemblerPredicate = isVI;
}
// Execpt for the NONE field, this must be kept in sync with the
@@ -1037,7 +1045,7 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _si : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
EXPe {
- let AssemblerPredicates = [isGFX6GFX7];
+ let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
@@ -1045,7 +1053,7 @@ multiclass EXP_m<bit done, SDPatternOperator node> {
def _vi : EXP_Helper<done>,
SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
EXPe_vi {
- let AssemblerPredicates = [isGFX8Plus];
+ let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index feebf3ab0f1..88acebb8969 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1658,8 +1658,8 @@ multiclass Int16Med3Pat<Instruction med3Inst,
def : FPMed3Pat<f32, V_MED3_F32>;
-let OtherPredicates = [isGFX9Plus] in {
+let OtherPredicates = [isGFX9] in {
def : FP16Med3Pat<f16, V_MED3_F16>;
defm : Int16Med3Pat<V_MED3_I16, smin, smax, smax_oneuse, smin_oneuse>;
defm : Int16Med3Pat<V_MED3_U16, umin, umax, umax_oneuse, umin_oneuse>;
-} // End Predicates = [isGFX9Plus]
+} // End Predicates = [isGFX9]
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 7e0e134d71f..797586bbb54 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -284,18 +284,18 @@ defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
-let SubtargetPredicate = isGFX7Plus in {
+let SubtargetPredicate = isCIVI in {
def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
-} // let SubtargetPredicate = isGFX7Plus
+} // let SubtargetPredicate = isCIVI
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>;
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>;
-} // SubtargetPredicate = isGFX8Plus
+} // SubtargetPredicate = isVI
let SubtargetPredicate = HasFlatScratchInsts, Uses = [FLAT_SCR] in {
defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads <"s_scratch_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
@@ -367,7 +367,7 @@ defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_6
} // let SubtargetPredicate = HasScalarAtomics
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">;
defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
}
@@ -385,7 +385,7 @@ class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
- let AssemblerPredicates = [isGFX6GFX7];
+ let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
@@ -439,7 +439,7 @@ class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
, Enc64 {
bit glc;
- let AssemblerPredicates = [isGFX8Plus];
+ let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
@@ -628,7 +628,7 @@ class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
SM_Real<ps>,
Enc64 {
- let AssemblerPredicates = [isGFX7];
+ let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);
@@ -665,7 +665,7 @@ class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
- let AssemblerPredicates = [isGFX7];
+ let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
@@ -717,7 +717,7 @@ multiclass SMRD_Pattern <string Instr, ValueType vt> {
def : GCNPat <
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
(vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
- let OtherPredicates = [isGFX7];
+ let OtherPredicates = [isCIOnly];
}
// 3. SGPR offset
@@ -744,7 +744,7 @@ multiclass SMLoad_Pattern <string Instr, ValueType vt> {
def : GCNPat <
(vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
(!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc))> {
- let OtherPredicates = [isGFX7];
+ let OtherPredicates = [isCIOnly];
}
// 3. Offset loaded in an 32bit SGPR
@@ -778,18 +778,18 @@ defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX8", v8f32>;
defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16f32>;
} // End let AddedComplexity = 100
-let OtherPredicates = [isGFX6GFX7] in {
+let OtherPredicates = [isSICI] in {
def : GCNPat <
(i64 (readcyclecounter)),
(S_MEMTIME)
>;
}
-let OtherPredicates = [isGFX8Plus] in {
+let OtherPredicates = [isVI] in {
def : GCNPat <
(i64 (readcyclecounter)),
(S_MEMREALTIME)
>;
-} // let OtherPredicates = [isGFX8Plus]
+} // let OtherPredicates = [isVI]
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index a017058ac95..1cb9f27dd02 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -253,7 +253,7 @@ def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {
}
}
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {
def S_ANDN1_SAVEEXEC_B64 : SOP1_64<"s_andn1_saveexec_b64">;
def S_ORN1_SAVEEXEC_B64 : SOP1_64<"s_orn1_saveexec_b64">;
@@ -262,7 +262,7 @@ let SubtargetPredicate = isGFX9Plus in {
} // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]
def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32">;
-} // End SubtargetPredicate = isGFX9Plus
+} // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===//
// SOP2 Instructions
@@ -518,7 +518,7 @@ let Defs = [SCC] in {
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
} // End Defs = [SCC]
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def S_RFE_RESTORE_B64 : SOP2_Pseudo <
"s_rfe_restore_b64", (outs),
(ins SSrc_b64:$src0, SSrc_b32:$src1),
@@ -529,7 +529,7 @@ let SubtargetPredicate = isGFX8Plus in {
}
}
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
def S_PACK_LL_B32_B16 : SOP2_32<"s_pack_ll_b32_b16">;
def S_PACK_LH_B32_B16 : SOP2_32<"s_pack_lh_b32_b16">;
def S_PACK_HH_B32_B16 : SOP2_32<"s_pack_hh_b32_b16">;
@@ -719,7 +719,7 @@ def S_SETREG_IMM32_B32 : SOPK_Pseudo <
} // End hasSideEffects = 1
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
def S_CALL_B64 : SOPK_Pseudo<
"s_call_b64",
(outs SReg_64:$sdst),
@@ -811,7 +811,7 @@ def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">;
def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>;
def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;
}
@@ -866,7 +866,7 @@ def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
let isReturn = 1;
}
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
let simm16 = 0;
let isBarrier = 1;
@@ -874,12 +874,12 @@ def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
}
}
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
let isBarrier = 1, isReturn = 1, simm16 = 0 in {
def S_ENDPGM_ORDERED_PS_DONE :
SOPP<0x01e, (ins), "s_endpgm_ordered_ps_done">;
} // End isBarrier = 1, isReturn = 1, simm16 = 0
-} // End SubtargetPredicate = isGFX9Plus
+} // End SubtargetPredicate = isGFX9
let isBranch = 1, SchedRW = [WriteBranch] in {
def S_BRANCH : SOPP <
@@ -954,7 +954,7 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
let isConvergent = 1;
}
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def S_WAKEUP : SOPP <0x00000003, (ins), "s_wakeup"> {
let simm16 = 0;
let mayLoad = 1;
@@ -1111,7 +1111,7 @@ def : GCNPat <
class Select_si<string opName> :
SIMCInstr<opName, SIEncodingFamily.SI> {
- list<Predicate> AssemblerPredicates = [isGFX6GFX7];
+ list<Predicate> AssemblerPredicates = [isSICI];
string DecoderNamespace = "SICI";
}
@@ -1248,7 +1248,7 @@ def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>,
class Select_vi<string opName> :
SIMCInstr<opName, SIEncodingFamily.VI> {
- list<Predicate> AssemblerPredicates = [isGFX8Plus];
+ list<Predicate> AssemblerPredicates = [isVI];
string DecoderNamespace = "VI";
}
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index c9d0def343a..15006155d9b 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -303,7 +303,7 @@ defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>;
// These instruction only exist on SI and CI
-let SubtargetPredicate = isGFX6GFX7 in {
+let SubtargetPredicate = isSICI in {
let SchedRW = [WriteQuarterRate32] in {
defm V_LOG_CLAMP_F32 : VOP1Inst <"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>;
@@ -318,10 +318,10 @@ defm V_RCP_CLAMP_F64 : VOP1Inst <"v_rcp_clamp_f64", VOP_F64_F64>;
defm V_RSQ_CLAMP_F64 : VOP1Inst <"v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamp>;
} // End SchedRW = [WriteDouble]
-} // End SubtargetPredicate = isGFX6GFX7
+} // End SubtargetPredicate = isSICI
-let SubtargetPredicate = isGFX7Plus in {
+let SubtargetPredicate = isCIVI in {
let SchedRW = [WriteDoubleAdd] in {
defm V_TRUNC_F64 : VOP1Inst <"v_trunc_f64", VOP_F64_F64, ftrunc>;
@@ -335,7 +335,7 @@ defm V_LOG_LEGACY_F32 : VOP1Inst <"v_log_legacy_f32", VOP_F32_F32>;
defm V_EXP_LEGACY_F32 : VOP1Inst <"v_exp_legacy_f32", VOP_F32_F32>;
} // End SchedRW = [WriteQuarterRate32]
-} // End SubtargetPredicate = isGFX7Plus
+} // End SubtargetPredicate = isCIVI
let SubtargetPredicate = Has16BitInsts in {
@@ -390,7 +390,7 @@ def VOP_SWAP_I32 : VOPProfile<[i32, i32, i32, untyped]> {
let Ins64 = (ins);
}
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
let Constraints = "$vdst = $src1, $vdst1 = $src0",
DisableEncoding="$vdst1,$src1",
SchedRW = [Write64Bit, Write64Bit] in {
@@ -404,7 +404,7 @@ defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
-} // End SubtargetPredicate = isGFX9Plus
+} // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===//
// Target
@@ -415,7 +415,7 @@ defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
//===----------------------------------------------------------------------===//
multiclass VOP1_Real_si <bits<9> op> {
- let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI" in {
+ let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
def _e32_si :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
@@ -490,7 +490,7 @@ defm V_MOVRELSD_B32 : VOP1_Real_si <0x44>;
//===----------------------------------------------------------------------===//
multiclass VOP1_Real_ci <bits<9> op> {
- let AssemblerPredicates = [isGFX7], DecoderNamespace = "CI" in {
+ let AssemblerPredicates = [isCIOnly], DecoderNamespace = "CI" in {
def _e32_ci :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
@@ -521,7 +521,7 @@ class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
}
multiclass VOP1Only_Real_vi <bits<10> op> {
- let AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI" in {
+ let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
@@ -529,7 +529,7 @@ multiclass VOP1Only_Real_vi <bits<10> op> {
}
multiclass VOP1_Real_e32e64_vi <bits<10> op> {
- let AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI" in {
+ let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _e32_vi :
VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
@@ -646,7 +646,7 @@ def V_MOV_B32_indirect : VPseudoInstSI<(outs),
PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
getVOPSrc0ForVT<i32>.ret:$src0)> {
let VOP1 = 1;
- let SubtargetPredicate = isGFX8Plus;
+ let SubtargetPredicate = isVI;
}
// This is a pseudo variant of the v_movreld_b32 instruction in which the
@@ -669,7 +669,7 @@ def V_MOVRELD_B32_V4 : V_MOVRELD_B32_pseudo<VReg_128>;
def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo<VReg_256>;
def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo<VReg_512>;
-let OtherPredicates = [isGFX8Plus] in {
+let OtherPredicates = [isVI] in {
def : GCNPat <
(i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
@@ -709,14 +709,14 @@ def : GCNPat <
(EXTRACT_SUBREG $src, sub0)
>;
-} // End OtherPredicates = [isGFX8Plus]
+} // End OtherPredicates = [isVI]
//===----------------------------------------------------------------------===//
// GFX9
//===----------------------------------------------------------------------===//
multiclass VOP1_Real_gfx9 <bits<10> op> {
- let AssemblerPredicates = [isGFX9Plus], DecoderNamespace = "GFX9" in {
+ let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
defm NAME : VOP1_Real_e32e64_vi <op>;
}
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 89eff0b3e76..ee165515ce7 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -480,7 +480,7 @@ def : GCNPat<
>;
// These instructions only exist on SI and CI
-let SubtargetPredicate = isGFX6GFX7, Predicates = [isGFX6GFX7] in {
+let SubtargetPredicate = isSICI, Predicates = [isSICI] in {
defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
@@ -492,7 +492,7 @@ defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
} // End isCommutable = 1
-} // End let SubtargetPredicate = SICI, Predicates = [isGFX6GFX7]
+} // End let SubtargetPredicate = SICI, Predicates = [isSICI]
class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
GCNPat<
@@ -698,7 +698,7 @@ def : GCNPat<
// SI
//===----------------------------------------------------------------------===//
-let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI" in {
+let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
multiclass VOP2_Real_si <bits<6> op> {
def _si :
@@ -729,7 +729,7 @@ multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
}
-} // End AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI"
+} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>;
defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>;
@@ -804,7 +804,7 @@ class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
let Inst{31} = 0x0; //encoding
}
-let AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI" in {
+let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
multiclass VOP2_Real_MADK_vi <bits<6> op> {
def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -838,7 +838,7 @@ multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
VOP2_Real_e32_vi<op>,
VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
-} // End AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI"
+} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
multiclass VOP2_SDWA_Real <bits<6> op> {
def _sdwa_vi :
@@ -852,7 +852,7 @@ multiclass VOP2_SDWA9_Real <bits<6> op> {
VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
}
-let AssemblerPredicates = [isGFX8] in {
+let AssemblerPredicates = [isVIOnly] in {
multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
def _e32_vi :
@@ -885,7 +885,7 @@ multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName
}
}
-let AssemblerPredicates = [isGFX9Plus] in {
+let AssemblerPredicates = [isGFX9] in {
multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
def _e32_gfx9 :
@@ -941,7 +941,7 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
}
}
-} // AssemblerPredicates = [isGFX9Plus]
+} // AssemblerPredicates = [isGFX9]
multiclass VOP2_Real_e32e64_vi <bits<6> op> :
Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
@@ -1030,7 +1030,7 @@ defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
// Aliases to simplify matching of floating-point instructions that
// are VOP2 on SI and VOP3 on VI.
@@ -1050,7 +1050,7 @@ def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
-} // End SubtargetPredicate = isGFX8Plus
+} // End SubtargetPredicate = isVI
let SubtargetPredicate = HasDLInsts in {
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 9de05bdc5e6..babd0417ecc 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -386,21 +386,21 @@ def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I3
let SchedRW = [Write64Bit] in {
// These instructions only exist on SI and CI
-let SubtargetPredicate = isGFX6GFX7, Predicates = [isGFX6GFX7] in {
+let SubtargetPredicate = isSICI, Predicates = [isSICI] in {
def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, shl>;
def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, srl>;
def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, sra>;
def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
-} // End SubtargetPredicate = isGFX6GFX7, Predicates = [isGFX6GFX7]
+} // End SubtargetPredicate = isSICI, Predicates = [isSICI]
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
-} // End SubtargetPredicate = isGFX8Plus
+} // End SubtargetPredicate = isVI
} // End SchedRW = [Write64Bit]
-let Predicates = [isGFX8Plus] in {
+let Predicates = [isVI] in {
def : GCNPat <
(getDivergentFrag<shl>.ret i64:$x, i32:$y),
(V_LSHLREV_B64 $y, $x)
@@ -416,7 +416,7 @@ def : AMDGPUPat <
}
-let SubtargetPredicate = isGFX7Plus in {
+let SubtargetPredicate = isCIVI in {
let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
@@ -430,27 +430,27 @@ def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
} // End SchedRW = [WriteDouble, WriteSALU]
} // End isCommutable = 1
-} // End SubtargetPredicate = isGFX7Plus
+} // End SubtargetPredicate = isCIVI
def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
- let Predicates = [Has16BitInsts, isGFX8];
+ let Predicates = [Has16BitInsts, isVIOnly];
let FPDPRounding = 1;
}
def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
let renamedInGFX9 = 1;
- let Predicates = [Has16BitInsts, isGFX9Plus];
+ let Predicates = [Has16BitInsts, isGFX9];
let FPDPRounding = 1;
}
def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma> {
- let Predicates = [Has16BitInsts, isGFX8];
+ let Predicates = [Has16BitInsts, isVIOnly];
let FPDPRounding = 1;
}
def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, fma> {
let renamedInGFX9 = 1;
- let Predicates = [Has16BitInsts, isGFX9Plus];
+ let Predicates = [Has16BitInsts, isGFX9];
let FPDPRounding = 1;
}
@@ -474,14 +474,14 @@ def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i3
} // End FPDPRounding = 1
} // End renamedInGFX9 = 1
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> {
let FPDPRounding = 1;
}
def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
-} // End SubtargetPredicate = isGFX9Plus
+} // End SubtargetPredicate = isGFX9
let Uses = [M0, EXEC], FPDPRounding = 1 in {
def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>,
@@ -504,13 +504,13 @@ def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32
} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
-let SubtargetPredicate = isGFX8Plus in {
+let SubtargetPredicate = isVI in {
def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
-} // End SubtargetPredicate = isGFX8Plus
+} // End SubtargetPredicate = isVI
let Predicates = [Has16BitInsts] in {
@@ -559,7 +559,7 @@ class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
let PredicateCodeUsesOperands = 1;
}
-let SubtargetPredicate = isGFX9Plus in {
+let SubtargetPredicate = isGFX9 in {
def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
@@ -609,7 +609,7 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>;
def : ThreeOp_i32_Pats<or, or, V_OR3_B32>;
def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;
-} // End SubtargetPredicate = isGFX9Plus
+} // End SubtargetPredicate = isGFX9
//===----------------------------------------------------------------------===//
// Integer Clamp Patterns
@@ -659,7 +659,7 @@ def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
// SI
//===----------------------------------------------------------------------===//
-let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI" in {
+let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
multiclass VOP3_Real_si<bits<9> op> {
def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
@@ -671,7 +671,7 @@ multiclass VOP3be_Real_si<bits<9> op> {
VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
-} // End AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI"
+} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
defm V_MAD_F32 : VOP3_Real_si <0x141>;
@@ -733,7 +733,7 @@ defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
multiclass VOP3_Real_ci<bits<9> op> {
def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
- let AssemblerPredicates = [isGFX7];
+ let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
}
}
@@ -741,7 +741,7 @@ multiclass VOP3_Real_ci<bits<9> op> {
multiclass VOP3be_Real_ci<bits<9> op> {
def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
- let AssemblerPredicates = [isGFX7];
+ let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
}
}
@@ -755,7 +755,7 @@ defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>;
// VI
//===----------------------------------------------------------------------===//
-let AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI" in {
+let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
multiclass VOP3_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -777,9 +777,9 @@ multiclass VOP3Interp_Real_vi<bits<10> op> {
VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
}
-} // End AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI"
+} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
-let AssemblerPredicates = [isGFX8], DecoderNamespace = "VI" in {
+let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
multiclass VOP3_F16_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
@@ -791,9 +791,9 @@ multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
-} // End AssemblerPredicates = [isGFX8], DecoderNamespace = "VI"
+} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
-let AssemblerPredicates = [isGFX9Plus], DecoderNamespace = "GFX9" in {
+let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
@@ -827,7 +827,7 @@ multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
}
}
-} // End AssemblerPredicates = [isGFX9Plus], DecoderNamespace = "GFX9"
+} // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 67be87428df..9d610610855 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -306,7 +306,7 @@ defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;
-let SubtargetPredicate = isGFX6GFX7 in {
+let SubtargetPredicate = isSICI in {
defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
@@ -376,7 +376,7 @@ defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
-} // End SubtargetPredicate = isGFX6GFX7
+} // End SubtargetPredicate = isSICI
let SubtargetPredicate = Has16BitInsts in {
@@ -702,7 +702,7 @@ def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;
//===----------------------------------------------------------------------===//
multiclass VOPC_Real_si <bits<9> op> {
- let AssemblerPredicates = [isGFX6GFX7], DecoderNamespace = "SICI" in {
+ let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
def _e32_si :
VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
VOPCe<op{7-0}>;
@@ -718,7 +718,7 @@ multiclass VOPC_Real_si <bits<9> op> {
}
def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"),
!cast<Instruction>(NAME#"_e32_si")> {
- let AssemblerPredicate = isGFX6GFX7;
+ let AssemblerPredicate = isSICI;
}
}
@@ -940,7 +940,7 @@ defm V_CMPX_CLASS_F64 : VOPC_Real_si <0xb8>;
//===----------------------------------------------------------------------===//
multiclass VOPC_Real_vi <bits<10> op> {
- let AssemblerPredicates = [isGFX8Plus], DecoderNamespace = "VI" in {
+ let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
def _e32_vi :
VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
VOPCe<op{7-0}>;
@@ -965,7 +965,7 @@ multiclass VOPC_Real_vi <bits<10> op> {
def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"),
!cast<Instruction>(NAME#"_e32_vi")> {
- let AssemblerPredicate = isGFX8Plus;
+ let AssemblerPredicate = isVI;
}
}
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