diff options
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 17 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/simd-arith.ll | 49 |
2 files changed, 66 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 2ea5c8d97a0..afde9ec63cb 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -118,6 +118,18 @@ multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> { defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>; defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>; } +multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> { + defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), + (outs), (ins), + [(set + (vec_t V128:$dst), + (vec_t (xor + (vec_t V128:$vec), + (vec_t (splat_pat (lane_t -1))) + )) + )], + "v128.not\t$dst, $vec", "v128.not", 62>; +} let Defs = [ARGUMENTS] in { defm "" : ConstVec<v16i8, @@ -203,6 +215,11 @@ defm OR : SIMDBitwise<or, "or", 60>; defm XOR : SIMDBitwise<xor, "xor", 61>; } // isCommutable = 1 +defm "" : SIMDNot<v16i8, splat16, i32>; +defm "" : SIMDNot<v8i16, splat8, i32>; +defm "" : SIMDNot<v4i32, splat4, i32>; +defm "" : SIMDNot<v2i64, splat2, i64>; + } // Defs = [ARGUMENTS] // follow convention of making implicit expansions unsigned diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll index ed927340818..3f2e4de3ed0 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll @@ -79,6 +79,20 @@ define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) { ret <16 x i8> %a } +; CHECK-LABEL: not_v16i8 +; NO-SIMD128-NOT: v128 +; SIMD128: .param v128{{$}} +; SIMD128: .result v128{{$}} +; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}} +; SIMD128: return $pop0 # +define <16 x i8> @not_v16i8(<16 x i8> %x) { + %a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + ret <16 x i8> %a +} + ; ============================================================================== ; 8 x i16 ; ============================================================================== @@ -148,6 +162,18 @@ define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) { ret <8 x i16> %a } +; CHECK-LABEL: not_v8i16 +; NO-SIMD128-NOT: v128 +; SIMD128: .param v128{{$}} +; SIMD128: .result v128{{$}} +; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}} +; SIMD128: return $pop0 # +define <8 x i16> @not_v8i16(<8 x i16> %x) { + %a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + ret <8 x i16> %a +} + ; ============================================================================== ; 4 x i32 ; ============================================================================== @@ -217,6 +243,17 @@ define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) { ret <4 x i32> %a } +; CHECK-LABEL: not_v4i32 +; NO-SIMD128-NOT: v128 +; SIMD128: .param v128{{$}} +; SIMD128: .result v128{{$}} +; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}} +; SIMD128: return $pop0 # +define <4 x i32> @not_v4i32(<4 x i32> %x) { + %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %a +} + ; ============================================================================== ; 2 x i64 ; ============================================================================== @@ -289,6 +326,18 @@ define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) { ret <2 x i64> %a } +; CHECK-LABEL: not_v2i64 +; NO-SIMD128-NOT: v128 +; SIMD128-VM-NOT: v128 +; SIMD128: .param v128{{$}} +; SIMD128: .result v128{{$}} +; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}} +; SIMD128: return $pop0 # +define <2 x i64> @not_v2i64(<2 x i64> %x) { + %a = xor <2 x i64> %x, <i64 -1, i64 -1> + ret <2 x i64> %a +} + ; ============================================================================== ; 4 x float ; ============================================================================== |
