diff options
48 files changed, 110 insertions, 1126 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 24a1386d2f0..be845e13d47 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -179,23 +179,11 @@ def CondCode : AsmOperandClass { // A 32-bit register pasrsed as 64-bit def GPR32as64Operand : AsmOperandClass { let Name = "GPR32as64"; - let ParserMethod = - "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSubReg>"; } def GPR32as64 : RegisterOperand<GPR32> { let ParserMatchClass = GPR32as64Operand; } -// A 64-bit register pasrsed as 32-bit -def GPR64as32Operand : AsmOperandClass { - let Name = "GPR64as32"; - let ParserMethod = - "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSuperReg>"; -} -def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> { - let ParserMatchClass = GPR64as32Operand; -} - // 8-bit immediate for AdvSIMD where 64-bit values of the form: // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh // are encoded as the eight bit value 'abcdefgh'. diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 536c55bf764..8032f50eef9 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -527,37 +527,21 @@ let Predicates = [HasSVE] in { defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">; defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">; - defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">; - defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">; - defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">; - defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">; defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">; defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">; defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">; defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">; - defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">; - defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">; - defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">; - defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">; defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">; defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">; defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">; defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">; - defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">; - defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">; - defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">; - defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">; defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">; defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">; defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">; defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">; - defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">; - defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">; - defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">; - defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">; defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">; defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">; defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index d042370acf4..5736802affe 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -66,12 +66,6 @@ enum class RegKind { SVEPredicateVector }; -enum RegConstraintEqualityTy { - EqualsReg, - EqualsSuperReg, - EqualsSubReg -}; - class AArch64AsmParser : public MCTargetAsmParser { private: StringRef Mnemonic; ///< Instruction mnemonic. @@ -98,8 +92,7 @@ private: bool parseOperand(OperandVector &Operands, bool isCondCode, bool invertCondCode); - bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo, - OperandVector &Operands); + bool showMatchError(SMLoc Loc, unsigned ErrCode, OperandVector &Operands); bool parseDirectiveArch(SMLoc L); bool parseDirectiveCPU(SMLoc L); @@ -146,8 +139,7 @@ private: bool tryParseNeonVectorRegister(OperandVector &Operands); OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands); OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands); - template <bool ParseShiftExtend, - RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg> + template <bool ParseShiftExtend> OperandMatchResultTy tryParseGPROperand(OperandVector &Operands); template <bool ParseShiftExtend, bool ParseSuffix> OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands); @@ -185,8 +177,6 @@ public: setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); } - bool regsEqual(const MCParsedAsmOperand &Op1, - const MCParsedAsmOperand &Op2) const override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; @@ -241,10 +231,6 @@ private: RegKind Kind; int ElementWidth; - // The register may be allowed as a different register class, - // e.g. for GPR64as32 or GPR32as64. - RegConstraintEqualityTy EqualityTy; - // In some cases the shift/extend needs to be explicitly parsed together // with the register, rather than as a separate operand. This is needed // for addressing modes where the instruction as a whole dictates the @@ -460,11 +446,6 @@ public: return Reg.RegNum; } - RegConstraintEqualityTy getRegEqualityTy() const { - assert(Kind == k_Register && "Invalid access!"); - return Reg.EqualityTy; - } - unsigned getVectorListStart() const { assert(Kind == k_VectorList && "Invalid access!"); return VectorList.RegNum; @@ -573,16 +554,14 @@ public: return DiagnosticPredicateTy::NearMatch; } - DiagnosticPredicate isSVEPattern() const { + bool isSVEPattern() const { if (!isImm()) - return DiagnosticPredicateTy::NoMatch; + return false; auto *MCE = dyn_cast<MCConstantExpr>(getImm()); if (!MCE) - return DiagnosticPredicateTy::NoMatch; + return false; int64_t Val = MCE->getValue(); - if (Val >= 0 && Val < 32) - return DiagnosticPredicateTy::Match; - return DiagnosticPredicateTy::NearMatch; + return Val >= 0 && Val < 32; } bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const { @@ -1023,11 +1002,6 @@ public: AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); } - bool isGPR64as32() const { - return Kind == k_Register && Reg.Kind == RegKind::Scalar && - AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum); - } - bool isWSeqPair() const { return Kind == k_Register && Reg.Kind == RegKind::Scalar && AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains( @@ -1344,18 +1318,6 @@ public: Inst.addOperand(MCOperand::createReg(Reg)); } - void addGPR64as32Operands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands!"); - assert( - AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg())); - - const MCRegisterInfo *RI = Ctx.getRegisterInfo(); - uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister( - RI->getEncodingValue(getReg())); - - Inst.addOperand(MCOperand::createReg(Reg)); - } - template <int Width> void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const { unsigned Base; @@ -1706,7 +1668,6 @@ public: static std::unique_ptr<AArch64Operand> CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, - RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg, AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, unsigned ShiftAmount = 0, unsigned HasExplicitAmount = false) { @@ -1714,7 +1675,6 @@ public: Op->Reg.RegNum = RegNum; Op->Reg.Kind = Kind; Op->Reg.ElementWidth = 0; - Op->Reg.EqualityTy = EqTy; Op->Reg.ShiftExtend.Type = ExtTy; Op->Reg.ShiftExtend.Amount = ShiftAmount; Op->Reg.ShiftExtend.HasExplicitAmount = HasExplicitAmount; @@ -1732,7 +1692,7 @@ public: assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector || Kind == RegKind::SVEPredicateVector) && "Invalid vector kind"); - auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, + auto Op = CreateReg(RegNum, Kind, S, E, Ctx, ExtTy, ShiftAmount, HasExplicitAmount); Op->Reg.ElementWidth = ElementWidth; return Op; @@ -3204,7 +3164,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) { return MatchOperand_Success; } -template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy> +template <bool ParseShiftExtend> OperandMatchResultTy AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) { SMLoc StartLoc = getLoc(); @@ -3217,7 +3177,7 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) { // No shift/extend is the default. if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) { Operands.push_back(AArch64Operand::CreateReg( - RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy)); + RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext())); return MatchOperand_Success; } @@ -3231,10 +3191,10 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) { return Res; auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get()); - Operands.push_back(AArch64Operand::CreateReg( - RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy, - Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), - Ext->hasShiftExtendAmount())); + Operands.push_back(AArch64Operand::CreateReg(RegNum, RegKind::Scalar, + StartLoc, Ext->getEndLoc(), getContext(), + Ext->getShiftExtendType(), Ext->getShiftExtendAmount(), + Ext->hasShiftExtendAmount())); return MatchOperand_Success; } @@ -3452,30 +3412,6 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode, } } -bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1, - const MCParsedAsmOperand &Op2) const { - auto &AOp1 = static_cast<const AArch64Operand&>(Op1); - auto &AOp2 = static_cast<const AArch64Operand&>(Op2); - if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg && - AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg) - return MCTargetAsmParser::regsEqual(Op1, Op2); - - assert(AOp1.isScalarReg() && AOp2.isScalarReg() && - "Testing equality of non-scalar registers not supported"); - - // Check if a registers match their sub/super register classes. - if (AOp1.getRegEqualityTy() == EqualsSuperReg) - return getXRegFromWReg(Op1.getReg()) == Op2.getReg(); - if (AOp1.getRegEqualityTy() == EqualsSubReg) - return getWRegFromXReg(Op1.getReg()) == Op2.getReg(); - if (AOp2.getRegEqualityTy() == EqualsSuperReg) - return getXRegFromWReg(Op2.getReg()) == Op1.getReg(); - if (AOp2.getRegEqualityTy() == EqualsSubReg) - return getWRegFromXReg(Op2.getReg()) == Op1.getReg(); - - return false; -} - /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its /// operands. bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info, @@ -3829,22 +3765,10 @@ static std::string AArch64MnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID = 0); bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, - uint64_t ErrorInfo, OperandVector &Operands) { switch (ErrCode) { - case Match_InvalidTiedOperand: { - RegConstraintEqualityTy EqTy = - static_cast<const AArch64Operand &>(*Operands[ErrorInfo]) - .getRegEqualityTy(); - switch (EqTy) { - case RegConstraintEqualityTy::EqualsSubReg: - return Error(Loc, "operand must be 64-bit form of destination register"); - case RegConstraintEqualityTy::EqualsSuperReg: - return Error(Loc, "operand must be 32-bit form of destination register"); - case RegConstraintEqualityTy::EqualsReg: - return Error(Loc, "operand must match destination register"); - } - } + case Match_InvalidTiedOperand: + return Error(Loc, "operand must match destination register"); case Match_MissingFeature: return Error(Loc, "instruction requires a CPU feature not currently enabled"); @@ -4465,7 +4389,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return Error(IDLoc, Msg); } case Match_MnemonicFail: - return showMatchError(IDLoc, MatchResult, ErrorInfo, Operands); + return showMatchError(IDLoc, MatchResult, Operands); case Match_InvalidOperand: { SMLoc ErrorLoc = IDLoc; @@ -4484,7 +4408,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, ((AArch64Operand &)*Operands[ErrorInfo]).isTokenSuffix()) MatchResult = Match_InvalidSuffix; - return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands); + return showMatchError(ErrorLoc, MatchResult, Operands); } case Match_InvalidTiedOperand: case Match_InvalidMemoryIndexed1: @@ -4622,7 +4546,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc(); if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; - return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands); + return showMatchError(ErrorLoc, MatchResult, Operands); } } diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp index 626c580663f..8f4fca71800 100644 --- a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp @@ -1527,10 +1527,3 @@ void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum, unsigned Val = MI->getOperand(OpNum).getImm(); O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr); } - -void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - unsigned Reg = MI->getOperand(OpNum).getReg(); - O << getRegisterName(getWRegFromXReg(Reg)); -} diff --git a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h index 8dc9264f94a..15cb363dd3f 100644 --- a/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h +++ b/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h @@ -180,8 +180,6 @@ protected: template <char = 0> void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); - void printGPR64as32(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); template <int Width> void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index ff56d5c593a..d4e41310f9e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -333,32 +333,9 @@ class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt, let Inst{9-5} = pattern; let Inst{4-0} = Rdn; - // Signed 32bit forms require their GPR operand printed. - let AsmString = !if(!eq(opc{2,0}, 0b00), - !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"), - !strconcat(asm, "\t$Rdn, $pattern, mul $imm4")); - let Constraints = "$Rdn = $_Rdn"; } -multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> { - def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>; - - def : InstAlias<asm # "\t$Rd, $Rn, $pattern", - (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>; - def : InstAlias<asm # "\t$Rd, $Rn", - (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>; -} - -multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> { - def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>; - - def : InstAlias<asm # "\t$Rdn, $pattern", - (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>; - def : InstAlias<asm # "\t$Rdn", - (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>; -} - multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> { def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>; diff --git a/llvm/test/MC/AArch64/SVE/decb-diagnostics.s b/llvm/test/MC/AArch64/SVE/decb-diagnostics.s index 4f888bc884d..2f241a9979f 100644 --- a/llvm/test/MC/AArch64/SVE/decb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/decb-diagnostics.s @@ -37,12 +37,12 @@ decb x0, all, mul #17 // Invalid predicate patterns decb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: decb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/decd-diagnostics.s b/llvm/test/MC/AArch64/SVE/decd-diagnostics.s index db7c0cf80b0..8df9e8a8cce 100644 --- a/llvm/test/MC/AArch64/SVE/decd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/decd-diagnostics.s @@ -37,12 +37,12 @@ decd x0, all, mul #17 // Invalid predicate patterns decd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: decd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/dech-diagnostics.s b/llvm/test/MC/AArch64/SVE/dech-diagnostics.s index bb7d1ef43fa..1263f963254 100644 --- a/llvm/test/MC/AArch64/SVE/dech-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/dech-diagnostics.s @@ -37,12 +37,12 @@ dech x0, all, mul #17 // Invalid predicate patterns dech x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: dech x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: dech x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: dech x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/decw-diagnostics.s b/llvm/test/MC/AArch64/SVE/decw-diagnostics.s index 7ecf9e06bd3..1634e62b34a 100644 --- a/llvm/test/MC/AArch64/SVE/decw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/decw-diagnostics.s @@ -37,12 +37,12 @@ decw x0, all, mul #17 // Invalid predicate patterns decw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: decw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: decw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/incb-diagnostics.s b/llvm/test/MC/AArch64/SVE/incb-diagnostics.s index 9f20018ae00..df5215e16e7 100644 --- a/llvm/test/MC/AArch64/SVE/incb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/incb-diagnostics.s @@ -37,12 +37,12 @@ incb x0, all, mul #17 // Invalid predicate patterns incb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: incb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/incd-diagnostics.s b/llvm/test/MC/AArch64/SVE/incd-diagnostics.s index 75337ec8583..1e53ee6c31a 100644 --- a/llvm/test/MC/AArch64/SVE/incd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/incd-diagnostics.s @@ -37,12 +37,12 @@ incd x0, all, mul #17 // Invalid predicate patterns incd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: incd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/inch-diagnostics.s b/llvm/test/MC/AArch64/SVE/inch-diagnostics.s index 00fea15f7b7..dea84fbd5c0 100644 --- a/llvm/test/MC/AArch64/SVE/inch-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/inch-diagnostics.s @@ -37,12 +37,12 @@ inch x0, all, mul #17 // Invalid predicate patterns inch x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: inch x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: inch x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: inch x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/incw-diagnostics.s b/llvm/test/MC/AArch64/SVE/incw-diagnostics.s index d5b6e71c942..a5df210a707 100644 --- a/llvm/test/MC/AArch64/SVE/incw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/incw-diagnostics.s @@ -37,12 +37,12 @@ incw x0, all, mul #17 // Invalid predicate patterns incw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: incw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ptrue-diagnostics.s b/llvm/test/MC/AArch64/SVE/ptrue-diagnostics.s index 51001265acb..d41e9a6a5f8 100644 --- a/llvm/test/MC/AArch64/SVE/ptrue-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ptrue-diagnostics.s @@ -5,12 +5,12 @@ // --------------------------------------------------------------------------// ptrue p0.s, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: ptrue p0.s, vl512 // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: ptrue p0.s, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: ptrue p0.s, vl9 // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ptrues-diagnostics.s b/llvm/test/MC/AArch64/SVE/ptrues-diagnostics.s index dfbf9794cae..0ba2d8344f9 100644 --- a/llvm/test/MC/AArch64/SVE/ptrues-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ptrues-diagnostics.s @@ -5,12 +5,12 @@ // --------------------------------------------------------------------------// ptrues p0.s, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: ptrues p0.s, vl512 // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: ptrues p0.s, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: ptrues p0.s, vl9 // CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s index 3bfe64b437c..92527fe068a 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s @@ -20,20 +20,6 @@ sqdecb sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqdecb x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqdecb x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdecb x0, x1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqdecb x0, x1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqdecb x0, all, mul #-1 @@ -56,12 +42,12 @@ sqdecb x0, all, mul #17 // Invalid predicate patterns sqdecb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqdecb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqdecb.s b/llvm/test/MC/AArch64/SVE/sqdecb.s index 570c3331e07..4cb6da9b8e7 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecb.s +++ b/llvm/test/MC/AArch64/SVE/sqdecb.s @@ -37,47 +37,6 @@ sqdecb x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqdecb x0, w0 -// CHECK-INST: sqdecb x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 20 04 <unknown> - -sqdecb x0, w0, all -// CHECK-INST: sqdecb x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 20 04 <unknown> - -sqdecb x0, w0, all, mul #1 -// CHECK-INST: sqdecb x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 20 04 <unknown> - -sqdecb x0, w0, all, mul #16 -// CHECK-INST: sqdecb x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 2f 04 <unknown> - -sqdecb x0, w0, pow2 -// CHECK-INST: sqdecb x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf8,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 20 04 <unknown> - -sqdecb x0, w0, pow2, mul #16 -// CHECK-INST: sqdecb x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 2f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s index ab1331fe6da..46b43a31bb8 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqdecd-diagnostics.s @@ -20,20 +20,6 @@ sqdecd sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqdecd x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqdecd x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdecd x0, x1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqdecd x0, x1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqdecd x0, all, mul #-1 @@ -56,12 +42,12 @@ sqdecd x0, all, mul #17 // Invalid predicate patterns sqdecd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqdecd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqdecd.s b/llvm/test/MC/AArch64/SVE/sqdecd.s index a5b9a72e3f1..00338533c1c 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecd.s +++ b/llvm/test/MC/AArch64/SVE/sqdecd.s @@ -37,47 +37,6 @@ sqdecd x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqdecd x0, w0 -// CHECK-INST: sqdecd x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb e0 04 <unknown> - -sqdecd x0, w0, all -// CHECK-INST: sqdecd x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb e0 04 <unknown> - -sqdecd x0, w0, all, mul #1 -// CHECK-INST: sqdecd x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb e0 04 <unknown> - -sqdecd x0, w0, all, mul #16 -// CHECK-INST: sqdecd x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb ef 04 <unknown> - -sqdecd x0, w0, pow2 -// CHECK-INST: sqdecd x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 e0 04 <unknown> - -sqdecd x0, w0, pow2, mul #16 -// CHECK-INST: sqdecd x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf8,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 ef 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s index 5ec208d22fd..b85cd699cbd 100644 --- a/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqdech-diagnostics.s @@ -20,20 +20,6 @@ sqdech sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqdech x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqdech x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdech x0, x1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqdech x0, x1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqdech x0, all, mul #-1 @@ -56,12 +42,12 @@ sqdech x0, all, mul #17 // Invalid predicate patterns sqdech x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdech x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqdech x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdech x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqdech.s b/llvm/test/MC/AArch64/SVE/sqdech.s index d6e52a85c5c..c58599a6938 100644 --- a/llvm/test/MC/AArch64/SVE/sqdech.s +++ b/llvm/test/MC/AArch64/SVE/sqdech.s @@ -37,47 +37,6 @@ sqdech x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqdech x0, w0 -// CHECK-INST: sqdech x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 60 04 <unknown> - -sqdech x0, w0, all -// CHECK-INST: sqdech x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 60 04 <unknown> - -sqdech x0, w0, all, mul #1 -// CHECK-INST: sqdech x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 60 04 <unknown> - -sqdech x0, w0, all, mul #16 -// CHECK-INST: sqdech x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb 6f 04 <unknown> - -sqdech x0, w0, pow2 -// CHECK-INST: sqdech x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf8,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 60 04 <unknown> - -sqdech x0, w0, pow2, mul #16 -// CHECK-INST: sqdech x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 6f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s index 006462838c9..bfea93b4be4 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqdecw-diagnostics.s @@ -20,20 +20,6 @@ sqdecw sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqdecw x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqdecw x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdecw x0, x1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqdecw x0, x1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqdecw x0, all, mul #-1 @@ -56,12 +42,12 @@ sqdecw x0, all, mul #17 // Invalid predicate patterns sqdecw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqdecw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqdecw.s b/llvm/test/MC/AArch64/SVE/sqdecw.s index 07706d80079..26c5ef90df6 100644 --- a/llvm/test/MC/AArch64/SVE/sqdecw.s +++ b/llvm/test/MC/AArch64/SVE/sqdecw.s @@ -37,47 +37,6 @@ sqdecw x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqdecw x0, w0 -// CHECK-INST: sqdecw x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb a0 04 <unknown> - -sqdecw x0, w0, all -// CHECK-INST: sqdecw x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb a0 04 <unknown> - -sqdecw x0, w0, all, mul #1 -// CHECK-INST: sqdecw x0, w0 -// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb a0 04 <unknown> - -sqdecw x0, w0, all, mul #16 -// CHECK-INST: sqdecw x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 fb af 04 <unknown> - -sqdecw x0, w0, pow2 -// CHECK-INST: sqdecw x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 a0 04 <unknown> - -sqdecw x0, w0, pow2, mul #16 -// CHECK-INST: sqdecw x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f8 af 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s index a780b27c58e..3c16c3538ee 100644 --- a/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqincb-diagnostics.s @@ -20,20 +20,6 @@ sqincb sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqincb x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqincb x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqincb x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqincb x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqincb x0, all, mul #-1 @@ -56,12 +42,12 @@ sqincb x0, all, mul #17 // Invalid predicate patterns sqincb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqincb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqincb.s b/llvm/test/MC/AArch64/SVE/sqincb.s index 8a3d3566b0a..5d261a0a948 100644 --- a/llvm/test/MC/AArch64/SVE/sqincb.s +++ b/llvm/test/MC/AArch64/SVE/sqincb.s @@ -37,47 +37,6 @@ sqincb x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqincb x0, w0 -// CHECK-INST: sqincb x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 20 04 <unknown> - -sqincb x0, w0, all -// CHECK-INST: sqincb x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 20 04 <unknown> - -sqincb x0, w0, all, mul #1 -// CHECK-INST: sqincb x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 20 04 <unknown> - -sqincb x0, w0, all, mul #16 -// CHECK-INST: sqincb x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 2f 04 <unknown> - -sqincb x0, w0, pow2 -// CHECK-INST: sqincb x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf0,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 20 04 <unknown> - -sqincb x0, w0, pow2, mul #16 -// CHECK-INST: sqincb x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 2f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s index f2541fb4f13..a6f382a78d9 100644 --- a/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqincd-diagnostics.s @@ -20,20 +20,6 @@ sqincd sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqincd x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqincd x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqincd x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqincd x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqincd x0, all, mul #-1 @@ -56,12 +42,12 @@ sqincd x0, all, mul #17 // Invalid predicate patterns sqincd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqincd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqincd.s b/llvm/test/MC/AArch64/SVE/sqincd.s index c74d6978c1f..37a4e335032 100644 --- a/llvm/test/MC/AArch64/SVE/sqincd.s +++ b/llvm/test/MC/AArch64/SVE/sqincd.s @@ -37,47 +37,6 @@ sqincd x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqincd x0, w0 -// CHECK-INST: sqincd x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 e0 04 <unknown> - -sqincd x0, w0, all -// CHECK-INST: sqincd x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 e0 04 <unknown> - -sqincd x0, w0, all, mul #1 -// CHECK-INST: sqincd x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 e0 04 <unknown> - -sqincd x0, w0, all, mul #16 -// CHECK-INST: sqincd x0, w0, all -// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 ef 04 <unknown> - -sqincd x0, w0, pow2 -// CHECK-INST: sqincd x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 e0 04 <unknown> - -sqincd x0, w0, pow2, mul #16 -// CHECK-INST: sqincd x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf0,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 ef 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s index 7e574d9710e..368fd4c60e6 100644 --- a/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqinch-diagnostics.s @@ -20,20 +20,6 @@ sqinch sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqinch x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqinch x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqinch x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqinch x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqinch x0, all, mul #-1 @@ -56,12 +42,12 @@ sqinch x0, all, mul #17 // Invalid predicate patterns sqinch x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqinch x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqinch x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqinch x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqinch.s b/llvm/test/MC/AArch64/SVE/sqinch.s index fd4befdbef0..a19dcee6949 100644 --- a/llvm/test/MC/AArch64/SVE/sqinch.s +++ b/llvm/test/MC/AArch64/SVE/sqinch.s @@ -37,47 +37,6 @@ sqinch x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqinch x0, w0 -// CHECK-INST: sqinch x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 60 04 <unknown> - -sqinch x0, w0, all -// CHECK-INST: sqinch x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 60 04 <unknown> - -sqinch x0, w0, all, mul #1 -// CHECK-INST: sqinch x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 60 04 <unknown> - -sqinch x0, w0, all, mul #16 -// CHECK-INST: sqinch x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 6f 04 <unknown> - -sqinch x0, w0, pow2 -// CHECK-INST: sqinch x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf0,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 60 04 <unknown> - -sqinch x0, w0, pow2, mul #16 -// CHECK-INST: sqinch x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 6f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s b/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s index 5176897f589..ab768d0cdde 100644 --- a/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/sqincw-diagnostics.s @@ -20,20 +20,6 @@ sqincw sp // ------------------------------------------------------------------------- // -// Operands not matching up - -sqincw x0, w1 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register -// CHECK-NEXT: sqincw x0, w1 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqincw x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: sqincw x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. sqincw x0, all, mul #-1 @@ -56,12 +42,12 @@ sqincw x0, all, mul #17 // Invalid predicate patterns sqincw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqincw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/sqincw.s b/llvm/test/MC/AArch64/SVE/sqincw.s index d21b16756bd..cc7e6d2e996 100644 --- a/llvm/test/MC/AArch64/SVE/sqincw.s +++ b/llvm/test/MC/AArch64/SVE/sqincw.s @@ -37,47 +37,6 @@ sqincw x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (x0, w0) and its aliases -// ---------------------------------------------------------------------------// - -sqincw x0, w0 -// CHECK-INST: sqincw x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 a0 04 <unknown> - -sqincw x0, w0, all -// CHECK-INST: sqincw x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 a0 04 <unknown> - -sqincw x0, w0, all, mul #1 -// CHECK-INST: sqincw x0, w0 -// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 a0 04 <unknown> - -sqincw x0, w0, all, mul #16 -// CHECK-INST: sqincw x0, w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f3 af 04 <unknown> - -sqincw x0, w0, pow2 -// CHECK-INST: sqincw x0, w0, pow2 -// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 a0 04 <unknown> - -sqincw x0, w0, pow2, mul #16 -// CHECK-INST: sqincw x0, w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f0 af 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s index fe73b92903f..002f30a6a4b 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqdecb-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqdecb w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqdecb w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqdecb wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqdecb wsp @@ -15,25 +20,6 @@ uqdecb sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned dec only has one register operand) - -uqdecb x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecb x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecb w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecb w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecb x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecb x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqdecb x0, all, mul #-1 @@ -56,12 +42,12 @@ uqdecb x0, all, mul #17 // Invalid predicate patterns uqdecb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqdecb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqdecb.s b/llvm/test/MC/AArch64/SVE/uqdecb.s index 4b4e0664fc1..6fe639c8a8f 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecb.s +++ b/llvm/test/MC/AArch64/SVE/uqdecb.s @@ -37,47 +37,6 @@ uqdecb x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqdecb w0 -// CHECK-INST: uqdecb w0 -// CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 20 04 <unknown> - -uqdecb w0, all -// CHECK-INST: uqdecb w0 -// CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 20 04 <unknown> - -uqdecb w0, all, mul #1 -// CHECK-INST: uqdecb w0 -// CHECK-ENCODING: [0xe0,0xff,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 20 04 <unknown> - -uqdecb w0, all, mul #16 -// CHECK-INST: uqdecb w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 2f 04 <unknown> - -uqdecb w0, pow2 -// CHECK-INST: uqdecb w0, pow2 -// CHECK-ENCODING: [0x00,0xfc,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc 20 04 <unknown> - -uqdecb w0, pow2, mul #16 -// CHECK-INST: uqdecb w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc 2f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s index 38134022c97..5e39897def5 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqdecd-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqdecd w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqdecd w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqdecd wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqdecd wsp @@ -15,25 +20,6 @@ uqdecd sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned dec only has one register operand) - -uqdecd x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecd x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecd w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecd w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecd x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecd x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqdecd x0, all, mul #-1 @@ -56,12 +42,12 @@ uqdecd x0, all, mul #17 // Invalid predicate patterns uqdecd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqdecd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqdecd.s b/llvm/test/MC/AArch64/SVE/uqdecd.s index ce8208cd6bf..fe5c6d24d93 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecd.s +++ b/llvm/test/MC/AArch64/SVE/uqdecd.s @@ -37,47 +37,6 @@ uqdecd x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqdecd w0 -// CHECK-INST: uqdecd w0 -// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff e0 04 <unknown> - -uqdecd w0, all -// CHECK-INST: uqdecd w0 -// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff e0 04 <unknown> - -uqdecd w0, all, mul #1 -// CHECK-INST: uqdecd w0 -// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff e0 04 <unknown> - -uqdecd w0, all, mul #16 -// CHECK-INST: uqdecd w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xff,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff ef 04 <unknown> - -uqdecd w0, pow2 -// CHECK-INST: uqdecd w0, pow2 -// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc e0 04 <unknown> - -uqdecd w0, pow2, mul #16 -// CHECK-INST: uqdecd w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xfc,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc ef 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s index 14a614f2210..26e415bd5a7 100644 --- a/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqdech-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqdech w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqdech w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqdech wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqdech wsp @@ -15,25 +20,6 @@ uqdech sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned dec only has one register operand) - -uqdech x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdech x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdech w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdech w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdech x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdech x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqdech x0, all, mul #-1 @@ -56,12 +42,12 @@ uqdech x0, all, mul #17 // Invalid predicate patterns uqdech x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdech x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqdech x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdech x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqdech.s b/llvm/test/MC/AArch64/SVE/uqdech.s index 5a3a63bcfd3..d751813ea12 100644 --- a/llvm/test/MC/AArch64/SVE/uqdech.s +++ b/llvm/test/MC/AArch64/SVE/uqdech.s @@ -37,47 +37,6 @@ uqdech x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqdech w0 -// CHECK-INST: uqdech w0 -// CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 60 04 <unknown> - -uqdech w0, all -// CHECK-INST: uqdech w0 -// CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 60 04 <unknown> - -uqdech w0, all, mul #1 -// CHECK-INST: uqdech w0 -// CHECK-ENCODING: [0xe0,0xff,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 60 04 <unknown> - -uqdech w0, all, mul #16 -// CHECK-INST: uqdech w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff 6f 04 <unknown> - -uqdech w0, pow2 -// CHECK-INST: uqdech w0, pow2 -// CHECK-ENCODING: [0x00,0xfc,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc 60 04 <unknown> - -uqdech w0, pow2, mul #16 -// CHECK-INST: uqdech w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc 6f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s index 4664393d839..56b6298138d 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqdecw-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqdecw w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqdecw w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqdecw wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqdecw wsp @@ -15,25 +20,6 @@ uqdecw sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned dec only has one register operand) - -uqdecw x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecw x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecw w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecw w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqdecw x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqdecw x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqdecw x0, all, mul #-1 @@ -56,12 +42,12 @@ uqdecw x0, all, mul #17 // Invalid predicate patterns uqdecw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqdecw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqdecw.s b/llvm/test/MC/AArch64/SVE/uqdecw.s index 61330702cd8..d4c168c0db9 100644 --- a/llvm/test/MC/AArch64/SVE/uqdecw.s +++ b/llvm/test/MC/AArch64/SVE/uqdecw.s @@ -37,47 +37,6 @@ uqdecw x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqdecw w0 -// CHECK-INST: uqdecw w0 -// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff a0 04 <unknown> - -uqdecw w0, all -// CHECK-INST: uqdecw w0 -// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff a0 04 <unknown> - -uqdecw w0, all, mul #1 -// CHECK-INST: uqdecw w0 -// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff a0 04 <unknown> - -uqdecw w0, all, mul #16 -// CHECK-INST: uqdecw w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 ff af 04 <unknown> - -uqdecw w0, pow2 -// CHECK-INST: uqdecw w0, pow2 -// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc a0 04 <unknown> - -uqdecw w0, pow2, mul #16 -// CHECK-INST: uqdecw w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 fc af 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s index 59940ca3252..a6fd75c2d24 100644 --- a/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqincb-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqincb w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqincb w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqincb wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqincb wsp @@ -15,25 +20,6 @@ uqincb sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned inc only has one register operand) - -uqincb x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincb x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincb w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincb w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincb x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincb x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqincb x0, all, mul #-1 @@ -56,12 +42,12 @@ uqincb x0, all, mul #17 // Invalid predicate patterns uqincb x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincb x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqincb x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincb x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqincb.s b/llvm/test/MC/AArch64/SVE/uqincb.s index 16c621c512a..f3529d388c4 100644 --- a/llvm/test/MC/AArch64/SVE/uqincb.s +++ b/llvm/test/MC/AArch64/SVE/uqincb.s @@ -37,47 +37,6 @@ uqincb x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqincb w0 -// CHECK-INST: uqincb w0 -// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 20 04 <unknown> - -uqincb w0, all -// CHECK-INST: uqincb w0 -// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 20 04 <unknown> - -uqincb w0, all, mul #1 -// CHECK-INST: uqincb w0 -// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 20 04 <unknown> - -uqincb w0, all, mul #16 -// CHECK-INST: uqincb w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 2f 04 <unknown> - -uqincb w0, pow2 -// CHECK-INST: uqincb w0, pow2 -// CHECK-ENCODING: [0x00,0xf4,0x20,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 20 04 <unknown> - -uqincb w0, pow2, mul #16 -// CHECK-INST: uqincb w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 2f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s index 54a22793f5a..a234c7b5882 100644 --- a/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqincd-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqincd w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqincd w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqincd wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqincd wsp @@ -15,25 +20,6 @@ uqincd sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned inc only has one register operand) - -uqincd x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincd x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincd w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincd w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincd x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincd x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqincd x0, all, mul #-1 @@ -56,12 +42,12 @@ uqincd x0, all, mul #17 // Invalid predicate patterns uqincd x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincd x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqincd x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincd x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqincd.s b/llvm/test/MC/AArch64/SVE/uqincd.s index fccfbadc5a5..4823f489f04 100644 --- a/llvm/test/MC/AArch64/SVE/uqincd.s +++ b/llvm/test/MC/AArch64/SVE/uqincd.s @@ -37,47 +37,6 @@ uqincd x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqincd w0 -// CHECK-INST: uqincd w0 -// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 e0 04 <unknown> - -uqincd w0, all -// CHECK-INST: uqincd w0 -// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 e0 04 <unknown> - -uqincd w0, all, mul #1 -// CHECK-INST: uqincd w0 -// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 e0 04 <unknown> - -uqincd w0, all, mul #16 -// CHECK-INST: uqincd w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 ef 04 <unknown> - -uqincd w0, pow2 -// CHECK-INST: uqincd w0, pow2 -// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 e0 04 <unknown> - -uqincd w0, pow2, mul #16 -// CHECK-INST: uqincd w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf4,0xef,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 ef 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s index 5f8761c4b6a..995ae22a7c5 100644 --- a/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqinch-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqinch w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqinch w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqinch wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqinch wsp @@ -15,25 +20,6 @@ uqinch sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned inc only has one register operand) - -uqinch x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqinch x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqinch w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqinch w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqinch x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqinch x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqinch x0, all, mul #-1 @@ -56,12 +42,12 @@ uqinch x0, all, mul #17 // Invalid predicate patterns uqinch x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqinch x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqinch x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqinch x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqinch.s b/llvm/test/MC/AArch64/SVE/uqinch.s index 26f76431f8a..5bffa14d6f4 100644 --- a/llvm/test/MC/AArch64/SVE/uqinch.s +++ b/llvm/test/MC/AArch64/SVE/uqinch.s @@ -37,47 +37,6 @@ uqinch x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqinch w0 -// CHECK-INST: uqinch w0 -// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 60 04 <unknown> - -uqinch w0, all -// CHECK-INST: uqinch w0 -// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 60 04 <unknown> - -uqinch w0, all, mul #1 -// CHECK-INST: uqinch w0 -// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 60 04 <unknown> - -uqinch w0, all, mul #16 -// CHECK-INST: uqinch w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 6f 04 <unknown> - -uqinch w0, pow2 -// CHECK-INST: uqinch w0, pow2 -// CHECK-ENCODING: [0x00,0xf4,0x60,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 60 04 <unknown> - -uqinch w0, pow2, mul #16 -// CHECK-INST: uqinch w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 6f 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// diff --git a/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s b/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s index cb85c4e7a2a..6a770d203ea 100644 --- a/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/uqincw-diagnostics.s @@ -3,6 +3,11 @@ // ------------------------------------------------------------------------- // // Invalid result register +uqincw w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: uqincw w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + uqincw wsp // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: uqincw wsp @@ -15,25 +20,6 @@ uqincw sp // ------------------------------------------------------------------------- // -// Operands not matching up (unsigned inc only has one register operand) - -uqincw x0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincw x0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincw w0, w0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincw w0, w0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -uqincw x0, x0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand -// CHECK-NEXT: uqincw x0, x0 -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - - -// ------------------------------------------------------------------------- // // Immediate not compatible with encode/decode function. uqincw x0, all, mul #-1 @@ -56,12 +42,12 @@ uqincw x0, all, mul #17 // Invalid predicate patterns uqincw x0, vl512 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincw x0, vl512 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: uqincw x0, vl9 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincw x0, vl9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uqincw.s b/llvm/test/MC/AArch64/SVE/uqincw.s index 1c6d9a88b0e..8bd35d1c4e5 100644 --- a/llvm/test/MC/AArch64/SVE/uqincw.s +++ b/llvm/test/MC/AArch64/SVE/uqincw.s @@ -37,47 +37,6 @@ uqincw x0, all, mul #16 // ---------------------------------------------------------------------------// -// Test 32-bit form (w0) and its aliases -// ---------------------------------------------------------------------------// - -uqincw w0 -// CHECK-INST: uqincw w0 -// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 a0 04 <unknown> - -uqincw w0, all -// CHECK-INST: uqincw w0 -// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 a0 04 <unknown> - -uqincw w0, all, mul #1 -// CHECK-INST: uqincw w0 -// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 a0 04 <unknown> - -uqincw w0, all, mul #16 -// CHECK-INST: uqincw w0, all, mul #16 -// CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: e0 f7 af 04 <unknown> - -uqincw w0, pow2 -// CHECK-INST: uqincw w0, pow2 -// CHECK-ENCODING: [0x00,0xf4,0xa0,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 a0 04 <unknown> - -uqincw w0, pow2, mul #16 -// CHECK-INST: uqincw w0, pow2, mul #16 -// CHECK-ENCODING: [0x00,0xf4,0xaf,0x04] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 f4 af 04 <unknown> - - -// ---------------------------------------------------------------------------// // Test all patterns for 64-bit form // ---------------------------------------------------------------------------// |
