diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/pr32545.ll | 22 |
2 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8a7a8904539..8f05c61a957 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3589,7 +3589,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { SDValue NewLoad(Load, 0); // Fold the AND away. NewLoad may get replaced immediately. - CombineTo(N, NewLoad); + CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); if (Load->getExtensionType() == ISD::EXTLOAD) { NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, diff --git a/llvm/test/CodeGen/ARM/pr32545.ll b/llvm/test/CodeGen/ARM/pr32545.ll new file mode 100644 index 00000000000..5bfb01b4598 --- /dev/null +++ b/llvm/test/CodeGen/ARM/pr32545.ll @@ -0,0 +1,22 @@ +; RUN: llc %s -o - | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7--linux-gnueabi" + +; CHECK: vld1.16 {[[DREG:d[0-9]+]][0]}, {{.*}} +; CHECK: vmovl.u8 [[QREG:q[0-9]+]], [[DREG]] +; CHECK: vmovl.u16 [[QREG]], [[DREG]] + +define void @f(i32 %dstStride, i8* %indvars.iv, <2 x i8>* %zz) { +entry: + br label %for.body + +for.body: + %tmp = load <2 x i8>, <2 x i8>* %zz, align 1 + %tmp1 = extractelement <2 x i8> %tmp, i32 0 + %.lhs.rhs = zext i8 %tmp1 to i32 + call void @g(i32 %.lhs.rhs) + br label %for.body +} + +declare void @g(i32) |
