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-rw-r--r--llvm/test/CodeGen/AArch64/uaddo.ll71
-rw-r--r--llvm/test/CodeGen/X86/codegen-prepare-uaddo.ll64
-rw-r--r--llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll60
3 files changed, 195 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/uaddo.ll b/llvm/test/CodeGen/AArch64/uaddo.ll
new file mode 100644
index 00000000000..981528afd0f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/uaddo.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+; PR31754
+
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_increment_alt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #1 // =1
+; CHECK-NEXT: add x8, x0, #1 // =1
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: str x8, [x1]
+; CHECK-NEXT: ret
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ %ov = icmp eq i64 %x, -1
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_increment_alt_dom:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #1 // =1
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: add x9, x0, #1 // =1
+; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: str x9, [x1]
+; CHECK-NEXT: ret
+ %ov = icmp eq i64 %x, -1
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_decrement_alt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0 // =0
+; CHECK-NEXT: sub x8, x0, #1 // =1
+; CHECK-NEXT: cset w0, ne
+; CHECK-NEXT: str x8, [x1]
+; CHECK-NEXT: ret
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ %ov = icmp ne i64 %x, 0
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_decrement_alt_dom:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, #0 // =0
+; CHECK-NEXT: cset w8, ne
+; CHECK-NEXT: sub x9, x0, #1 // =1
+; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: str x9, [x1]
+; CHECK-NEXT: ret
+ %ov = icmp ne i64 %x, 0
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-uaddo.ll b/llvm/test/CodeGen/X86/codegen-prepare-uaddo.ll
index 2bc13cc57d2..921f0da3b8d 100644
--- a/llvm/test/CodeGen/X86/codegen-prepare-uaddo.ll
+++ b/llvm/test/CodeGen/X86/codegen-prepare-uaddo.ll
@@ -267,4 +267,68 @@ define i1 @illegal_type(i17 %x, i17* %p) {
ret i1 %ov
}
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_increment_alt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: leaq 1(%rdi), %rax
+; CHECK-NEXT: movq %rax, (%rsi)
+; CHECK-NEXT: cmpq $-1, %rdi
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ %ov = icmp eq i64 %x, -1
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_increment_alt_dom:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpq $-1, %rdi
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: incq %rdi
+; CHECK-NEXT: movq %rdi, (%rsi)
+; CHECK-NEXT: retq
+ %ov = icmp eq i64 %x, -1
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_decrement_alt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: leaq -1(%rdi), %rax
+; CHECK-NEXT: movq %rax, (%rsi)
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: retq
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ %ov = icmp ne i64 %x, 0
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: uaddo_i64_decrement_alt_dom:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: decq %rdi
+; CHECK-NEXT: movq %rdi, (%rsi)
+; CHECK-NEXT: retq
+ %ov = icmp ne i64 %x, 0
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64)
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
index 4b0bafacaf4..177aee7c2c0 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/overflow-intrinsics.ll
@@ -158,6 +158,66 @@ define i1 @uaddo_i16_increment_noncanonical_3(i16 %x, i16* %p) {
ret i1 %ov
}
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_increment_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: @uaddo_i64_increment_alt(
+; CHECK-NEXT: [[A:%.*]] = add i64 [[X:%.*]], 1
+; CHECK-NEXT: store i64 [[A]], i64* [[P:%.*]]
+; CHECK-NEXT: [[OV:%.*]] = icmp eq i64 [[X]], -1
+; CHECK-NEXT: ret i1 [[OV]]
+;
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ %ov = icmp eq i64 %x, -1
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_increment_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: @uaddo_i64_increment_alt_dom(
+; CHECK-NEXT: [[OV:%.*]] = icmp eq i64 [[X:%.*]], -1
+; CHECK-NEXT: [[A:%.*]] = add i64 [[X]], 1
+; CHECK-NEXT: store i64 [[A]], i64* [[P:%.*]]
+; CHECK-NEXT: ret i1 [[OV]]
+;
+ %ov = icmp eq i64 %x, -1
+ %a = add i64 %x, 1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
+; The overflow check may be against the input rather than the sum.
+
+define i1 @uaddo_i64_decrement_alt(i64 %x, i64* %p) {
+; CHECK-LABEL: @uaddo_i64_decrement_alt(
+; CHECK-NEXT: [[A:%.*]] = add i64 [[X:%.*]], -1
+; CHECK-NEXT: store i64 [[A]], i64* [[P:%.*]]
+; CHECK-NEXT: [[OV:%.*]] = icmp ne i64 [[X]], 0
+; CHECK-NEXT: ret i1 [[OV]]
+;
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ %ov = icmp ne i64 %x, 0
+ ret i1 %ov
+}
+
+; Make sure insertion is done correctly based on dominance.
+
+define i1 @uaddo_i64_decrement_alt_dom(i64 %x, i64* %p) {
+; CHECK-LABEL: @uaddo_i64_decrement_alt_dom(
+; CHECK-NEXT: [[OV:%.*]] = icmp ne i64 [[X:%.*]], 0
+; CHECK-NEXT: [[A:%.*]] = add i64 [[X]], -1
+; CHECK-NEXT: store i64 [[A]], i64* [[P:%.*]]
+; CHECK-NEXT: ret i1 [[OV]]
+;
+ %ov = icmp ne i64 %x, 0
+ %a = add i64 %x, -1
+ store i64 %a, i64* %p
+ ret i1 %ov
+}
+
; No transform for illegal types.
define i1 @uaddo_i42_increment_illegal_type(i42 %x, i42* %p) {
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