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-rw-r--r--llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp1
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp54
-rw-r--r--llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll39
3 files changed, 34 insertions, 60 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index cb23f9b4815..dd759fe9ce5 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -57,7 +57,6 @@ namespace {
return *this;
}
OffsetRange &shift(int32_t S) {
- assert(alignTo(std::abs(S), Align) == uint64_t(std::abs(S)));
Min += S;
Max += S;
return *this;
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 177567306fe..e2edccbc8d1 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1472,58 +1472,32 @@ HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
auto *GAN = cast<GlobalAddressSDNode>(Op);
auto PtrVT = getPointerTy(DAG.getDataLayout());
- const GlobalValue *GV = GAN->getGlobal();
- int32_t Offset = GAN->getOffset();
- int32_t Addend = 0;
-
- unsigned GlobAlign = GV->getAlignment();
- if (GlobAlign != 0 && Offset % GlobAlign != 0) {
- unsigned MinAlign = GlobAlign;
- for (SDNode *U : GAN->uses()) {
- if (auto *M = dyn_cast<MemSDNode>(U))
- MinAlign = std::min(MinAlign, M->getAlignment());
- }
- assert(isPowerOf2_32(MinAlign));
- if (Offset % MinAlign != 0) {
- Addend = Offset & (MinAlign-1); // Always non-negative.
- Offset -= Addend;
- }
- }
+ auto *GV = GAN->getGlobal();
+ int64_t Offset = GAN->getOffset();
auto &HLOF = *HTM.getObjFileLowering();
Reloc::Model RM = HTM.getRelocationModel();
- SDValue Res;
if (RM == Reloc::Static) {
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
const GlobalObject *GO = GV->getBaseObject();
if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
- Res = DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
- else
- Res = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
- } else {
- bool UsePCRel = HTM.shouldAssumeDSOLocal(*GV->getParent(), GV);
- if (UsePCRel) {
- SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
- HexagonII::MO_PCREL);
- Res = DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
- } else {
- // Use GOT index.
- SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
- SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
- HexagonII::MO_GOT);
- SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
- Res = DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
- }
+ return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
+ return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
}
- assert(Res.getNode() != nullptr);
- if (Addend != 0) {
- SDValue A = DAG.getConstant(Addend, dl, MVT::i32);
- Res = DAG.getNode(ISD::ADD, dl, MVT::i32, Res, A);
+ bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
+ if (UsePCRel) {
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
+ HexagonII::MO_PCREL);
+ return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
}
- return Res;
+ // Use GOT index.
+ SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
+ SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
+ return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
}
// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
diff --git a/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll b/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll
index dba7a1ace2b..c479b949c6f 100644
--- a/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll
+++ b/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll
@@ -1,18 +1,10 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; This testcase checks that a valid offset is folded into a global address
-; when it's used in a load or a store instruction. The store in this code
-; is not really properly aligned (bugpoint output from a legal code), but
-; what's important is that the offset on the store instructions is a multiple
-; of the access size. In this case the actual address is @array+30, but that
-; value is not a multiple of 8, so it cannot appear as an immediate in memd.
-; Aside from the fact that @array+30 is not a valid address for memd, make
-; sure that in a memd instruction the offset field is a multiple of 8.
-
-; CHECK: r[[BASE:[0-9]+]] = #6
-; CHECK-DAG: memd(r[[BASE]]+##array+24)
-; CHECK-DAG: memd(r[[BASE]]+##array+32)
-
+; This should compile without errors, and the offsets with respect to the
+; beginning of the global "array" don't need to be multiples of 8.
+;
+; CHECK-DAG: memd(r0+##array+174)
+; CHECK-DAG: memd(r0+##array+182)
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
@@ -21,12 +13,21 @@ target triple = "hexagon"
define void @fred() #0 {
b0:
- %v1 = add nsw i32 0, -1
- %v2 = getelementptr inbounds [1000000 x i16], [1000000 x i16]* @array, i32 0, i32 %v1
- %v3 = getelementptr i16, i16* %v2, i32 16
- %v4 = bitcast i16* %v3 to <8 x i16>*
- store <8 x i16> zeroinitializer, <8 x i16>* %v4, align 8
- ret void
+ br i1 undef, label %b3, label %b1
+
+b1: ; preds = %b0
+ %v2 = add i32 0, 512
+ br label %b3
+
+b3: ; preds = %b1, %b0
+ %v4 = phi i32 [ 0, %b0 ], [ %v2, %b1 ]
+ %v5 = or i32 %v4, 1
+ %v6 = add nsw i32 %v5, -1
+ %v7 = getelementptr inbounds [1000000 x i16], [1000000 x i16]* @array, i32 0, i32 %v6
+ %v8 = getelementptr i16, i16* %v7, i32 88
+ %v9 = bitcast i16* %v8 to <8 x i16>*
+ store <8 x i16> zeroinitializer, <8 x i16>* %v9, align 8
+ unreachable
}
attributes #0 = { norecurse nounwind }
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