diff options
| -rw-r--r-- | llvm/include/llvm/Transforms/IPO/FunctionAttrs.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AVR/AVRInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 4 |
5 files changed, 7 insertions, 7 deletions
diff --git a/llvm/include/llvm/Transforms/IPO/FunctionAttrs.h b/llvm/include/llvm/Transforms/IPO/FunctionAttrs.h index 0c7713ab32f..85d6364c8bb 100644 --- a/llvm/include/llvm/Transforms/IPO/FunctionAttrs.h +++ b/llvm/include/llvm/Transforms/IPO/FunctionAttrs.h @@ -56,7 +56,7 @@ Pass *createPostOrderFunctionAttrsLegacyPass(); /// This pass provides a general RPO or "top down" propagation of /// function attributes. For a few (rare) cases, we can deduce significantly /// more about function attributes by working in RPO, so this pass -/// provides the compliment to the post-order pass above where the majority of +/// provides the complement to the post-order pass above where the majority of /// deduction is performed. // FIXME: Currently there is no RPO CGSCC pass structure to slide into and so // this is a boring module pass, but eventually it should be an RPO CGSCC pass diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td index bc66379ab70..693d80a1c06 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -694,7 +694,7 @@ Defs = [SREG] in } //===----------------------------------------------------------------------===// -// One's/Two's Compliment +// One's/Two's Complement //===----------------------------------------------------------------------===// let Constraints = "$src = $rd", Defs = [SREG] in @@ -1718,7 +1718,7 @@ Defs = [SREG] in (implicit SREG)]>; // CBR Rd, K - // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K. + // Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K. // FIXME: This uses the 'complement' encoder. We need it to also use the // imm_ldi8 encoder. This will cause no fixups to be created on this instruction. def CBRRdK : FRdK<0b0111, diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h index 5fa425c296a..4cee8d904c9 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h @@ -63,7 +63,7 @@ private: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; - /// Takes the compliment of a number (~0 - val). + /// Takes the complement of a number (~0 - val). unsigned encodeComplement(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td index 4f2bd61a279..2b847414b8a 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -517,7 +517,7 @@ multiclass ADD_SUB_i1<SDNode OpNode> { defm ADD_i1 : ADD_SUB_i1<add>; defm SUB_i1 : ADD_SUB_i1<sub>; -// int16, int32, and int64 signed addition. Since nvptx is 2's compliment, we +// int16, int32, and int64 signed addition. Since nvptx is 2's complement, we // also use these for unsigned arithmetic. defm ADD : I3<"add.s", add>; defm SUB : I3<"sub.s", sub>; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index f821bf75e44..1077121f8cb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -902,7 +902,7 @@ bool InstCombiner::WillNotOverflowSignedAdd(Value *LHS, Value *RHS, APInt RHSKnownOne(BitWidth, 0); computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI); - // Addition of two 2's compliment numbers having opposite signs will never + // Addition of two 2's complement numbers having opposite signs will never // overflow. if ((LHSKnownOne[BitWidth - 1] && RHSKnownZero[BitWidth - 1]) || (LHSKnownZero[BitWidth - 1] && RHSKnownOne[BitWidth - 1])) @@ -939,7 +939,7 @@ bool InstCombiner::WillNotOverflowSignedSub(Value *LHS, Value *RHS, APInt RHSKnownOne(BitWidth, 0); computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, 0, &CxtI); - // Subtraction of two 2's compliment numbers having identical signs will + // Subtraction of two 2's complement numbers having identical signs will // never overflow. if ((LHSKnownOne[BitWidth - 1] && RHSKnownOne[BitWidth - 1]) || (LHSKnownZero[BitWidth - 1] && RHSKnownZero[BitWidth - 1])) |
