diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 23 |
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 76f97b1ceaf..b6dc00f37b7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1763,6 +1763,10 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, get(TargetOpcode::COPY), CRReg) .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); + // Even if CR0 register were dead before, it is alive now since the + // instruction we just built uses it. + MI->clearRegisterDeads(PPC::CR0); + if (MIOpC != NewOpC) { // We need to be careful here: we're replacing one instruction with // another, and we need to make sure that we get all of the right diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll new file mode 100644 index 00000000000..3c3820951f2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -0,0 +1,23 @@ +; RUN: llc -print-before=peephole-opts -print-after=peephole-opts -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s + +define signext i32 @fn1(i32 %baz) { + %1 = mul nsw i32 %baz, 208 + %2 = zext i32 %1 to i64 + %3 = shl i64 %2, 48 + %4 = ashr exact i64 %3, 48 +; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>; +; CHECK: CMPLDI +; CHECK: BCC + +; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>; +; CHECK: COPY %CR0 +; CHECK: BCC + %5 = icmp eq i64 %4, 0 + br i1 %5, label %foo, label %bar + +foo: + ret i32 1 + +bar: + ret i32 0 +} |
