diff options
| -rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_round.ll | 22 |
2 files changed, 25 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index c3afa776c00..b3711adce04 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -687,6 +687,9 @@ void TargetLoweringBase::initActions() { // These operations default to expand. setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); + + // These library functions default to expand. + setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand); } // Most targets ignore the @llvm.prefetch intrinsic. @@ -711,7 +714,6 @@ void TargetLoweringBase::initActions() { setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); setOperationAction(ISD::FCEIL, MVT::f16, Expand); setOperationAction(ISD::FRINT, MVT::f16, Expand); - setOperationAction(ISD::FROUND, MVT::f16, Expand); setOperationAction(ISD::FTRUNC, MVT::f16, Expand); setOperationAction(ISD::FLOG , MVT::f32, Expand); setOperationAction(ISD::FLOG2, MVT::f32, Expand); @@ -722,7 +724,6 @@ void TargetLoweringBase::initActions() { setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); setOperationAction(ISD::FCEIL, MVT::f32, Expand); setOperationAction(ISD::FRINT, MVT::f32, Expand); - setOperationAction(ISD::FROUND, MVT::f32, Expand); setOperationAction(ISD::FTRUNC, MVT::f32, Expand); setOperationAction(ISD::FLOG , MVT::f64, Expand); setOperationAction(ISD::FLOG2, MVT::f64, Expand); @@ -733,7 +734,6 @@ void TargetLoweringBase::initActions() { setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); setOperationAction(ISD::FCEIL, MVT::f64, Expand); setOperationAction(ISD::FRINT, MVT::f64, Expand); - setOperationAction(ISD::FROUND, MVT::f64, Expand); setOperationAction(ISD::FTRUNC, MVT::f64, Expand); setOperationAction(ISD::FLOG , MVT::f128, Expand); setOperationAction(ISD::FLOG2, MVT::f128, Expand); @@ -744,7 +744,6 @@ void TargetLoweringBase::initActions() { setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); setOperationAction(ISD::FCEIL, MVT::f128, Expand); setOperationAction(ISD::FRINT, MVT::f128, Expand); - setOperationAction(ISD::FROUND, MVT::f128, Expand); setOperationAction(ISD::FTRUNC, MVT::f128, Expand); // Default ISD::TRAP to expand (which turns it into abort). diff --git a/llvm/test/CodeGen/X86/vec_round.ll b/llvm/test/CodeGen/X86/vec_round.ll new file mode 100644 index 00000000000..baa2f58631d --- /dev/null +++ b/llvm/test/CodeGen/X86/vec_round.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=nehalem -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @use(<2 x double>) + +; CHECK-LABEL: @test +; CHECK callq round + +; Function Attrs: nounwind uwtable +define void @test() { +entry: + %tmp = call <2 x double> @llvm.round.v2f64(<2 x double> undef) + call void @use(<2 x double> %tmp) + ret void +} + +; Function Attrs: nounwind readonly +declare <2 x double> @llvm.round.v2f64(<2 x double>) #0 + +attributes #0 = { nounwind readonly } + |
