diff options
| -rw-r--r-- | llvm/lib/CodeGen/MachineLICM.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir | 32 |
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index d3a77ab4945..0ad3ef18e55 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -374,6 +374,10 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) { /// Return true if instruction stores to the specified frame. static bool InstructionStoresToFI(const MachineInstr *MI, int FI) { + // Check mayStore before memory operands so that e.g. DBG_VALUEs will return + // true since they have no memory operands. + if (!MI->mayStore()) + return false; // If we lost memory operands, conservatively assume that the instruction // writes to all slots. if (MI->memoperands_empty()) diff --git a/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir new file mode 100644 index 00000000000..c5d1a8f81fc --- /dev/null +++ b/llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir @@ -0,0 +1,32 @@ +# RUN: llc -mtriple=aarch64 -run-pass machinelicm -verify-machineinstrs -o - %s | FileCheck %s +--- +name: test +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64 } +stack: + - { id: 0, size: 8, type: spill-slot } +body: | + bb.0: + ; CHECK-LABEL: name: test + ; CHECK-LABEL: bb.0: + ; CHECK: $x2 = LDRXui %stack.0, 0 + liveins: $x0, $x1, $x2 + B %bb.1 + + bb.1: + ; CHECK-LABEL: bb.1: + ; CHECK-NOT: $x2 = LDRXui %stack.0, 0 + liveins: $x0 + DBG_VALUE %stack.0, 0 + $x2 = LDRXui %stack.0, 0 :: (load 8 from %stack.0) + $x0 = ADDXrr $x0, $x2 + $xzr = SUBSXri $x0, 1, 0, implicit-def $nzcv + Bcc 11, %bb.1, implicit $nzcv + B %bb.2 + + bb.2: + liveins: $x0 + %0 = COPY $x0 + %0 = COPY $x0 ; Force isSSA = false. +... |
