diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Processors.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600Packetizer.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/unknown-processor.ll | 20 |
5 files changed, 29 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 4c69cbdce44..63b19acea20 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -82,7 +82,9 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, TargetMachine &TM) : AMDGPUGenSubtargetInfo(TT, GPU, FS), DumpCode(false), R600ALUInst(false), HasVertexCache(false), - TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), + TexVTXClauseSize(0), + Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600), + FP64(false), FP64Denormals(false), FP32Denormals(false), FPExceptions(false), FastFMAF32(false), HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false), FlatForGlobal(false), EnableIRStructurizer(true), @@ -90,7 +92,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, EnableIfCvt(true), EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false), EnableXNACK(false), - WavefrontSize(0), CFALUBug(false), + WavefrontSize(64), CFALUBug(false), LocalMemorySize(0), MaxPrivateElementSize(0), EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 5a1652d160e..617ce097165 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -101,7 +101,7 @@ static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { if (TT.getArch() == Triple::amdgcn) return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti"; - return ""; + return "r600"; } static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { diff --git a/llvm/lib/Target/AMDGPU/Processors.td b/llvm/lib/Target/AMDGPU/Processors.td index 5903bdf96c4..f5f1eb14e99 100644 --- a/llvm/lib/Target/AMDGPU/Processors.td +++ b/llvm/lib/Target/AMDGPU/Processors.td @@ -13,11 +13,8 @@ class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Featur //===----------------------------------------------------------------------===// // R600 //===----------------------------------------------------------------------===// -def : Proc<"", R600_VLIW5_Itin, - [FeatureR600, FeatureVertexCache]>; - def : Proc<"r600", R600_VLIW5_Itin, - [FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>; + [FeatureR600, FeatureVertexCache, FeatureWavefrontSize64]>; def : Proc<"r630", R600_VLIW5_Itin, [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>; diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp index 964c65cd952..6a34df20fb1 100644 --- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp @@ -336,6 +336,9 @@ bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) { // DFA state table should not be empty. assert(Packetizer.getResourceTracker() && "Empty DFA table!"); + if (Packetizer.getResourceTracker()->getInstrItins()->isEmpty()) + return false; + // // Loop over all basic blocks and remove KILL pseudo-instructions // These instructions confuse the dependence analysis. Consider: diff --git a/llvm/test/CodeGen/AMDGPU/unknown-processor.ll b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll new file mode 100644 index 00000000000..941f4c601e3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/unknown-processor.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=amdgcn -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s +; RUN: llc -march=r600 -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s + +; Should not crash when the processor is not recognized and the +; wavefront size feature not set. + +; Should also not have fragments of r600 and gcn isa mixed. + +; ERROR: 'unknown' is not a recognized processor for this target (ignoring processor) + +; GCN-NOT: MOV +; GCN: buffer_store_dword +; GCN: ScratchSize: 8{{$}} + +; R600: MOV +define void @foo() { + %alloca = alloca i32, align 4 + store volatile i32 0, i32* %alloca + ret void +} |
