diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr30451.ll | 69 |
2 files changed, 80 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 1d9181b95d1..c414a1512e9 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -8507,8 +8507,17 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, if (BinOpcode) BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); if (CmpOpcode) { - BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) - .addReg(incr).addReg(dest); + // Signed comparisons of byte or halfword values must be sign-extended. + if (CmpOpcode == PPC::CMPW && AtomicSize < 4) { + unsigned ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); + BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH), + ExtReg).addReg(dest); + BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) + .addReg(incr).addReg(ExtReg); + } else + BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) + .addReg(incr).addReg(dest); + BuildMI(BB, dl, TII->get(PPC::BCC)) .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB); BB->addSuccessor(loop2MBB); diff --git a/llvm/test/CodeGen/PowerPC/pr30451.ll b/llvm/test/CodeGen/PowerPC/pr30451.ll new file mode 100644 index 00000000000..930553451cf --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr30451.ll @@ -0,0 +1,69 @@ +; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown | FileCheck %s +define i8 @atomic_min_i8() { + top: + %0 = alloca i8, align 2 + %1 = bitcast i8* %0 to i8* + call void @llvm.lifetime.start(i64 2, i8* %1) + store i8 -1, i8* %0, align 2 + %2 = atomicrmw min i8* %0, i8 0 acq_rel + %3 = load atomic i8, i8* %0 acquire, align 8 + call void @llvm.lifetime.end(i64 2, i8* %1) + ret i8 %3 +; CHECK-LABEL: atomic_min_i8 +; CHECK: lbarx [[DST:[0-9]+]], +; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]] +; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]] +; CHECK-NEXT: bge 0 +} +define i16 @atomic_min_i16() { + top: + %0 = alloca i16, align 2 + %1 = bitcast i16* %0 to i8* + call void @llvm.lifetime.start(i64 2, i8* %1) + store i16 -1, i16* %0, align 2 + %2 = atomicrmw min i16* %0, i16 0 acq_rel + %3 = load atomic i16, i16* %0 acquire, align 8 + call void @llvm.lifetime.end(i64 2, i8* %1) + ret i16 %3 +; CHECK-LABEL: atomic_min_i16 +; CHECK: lharx [[DST:[0-9]+]], +; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]] +; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]] +; CHECK-NEXT: bge 0 +} + +define i8 @atomic_max_i8() { + top: + %0 = alloca i8, align 2 + %1 = bitcast i8* %0 to i8* + call void @llvm.lifetime.start(i64 2, i8* %1) + store i8 -1, i8* %0, align 2 + %2 = atomicrmw max i8* %0, i8 0 acq_rel + %3 = load atomic i8, i8* %0 acquire, align 8 + call void @llvm.lifetime.end(i64 2, i8* %1) + ret i8 %3 +; CHECK-LABEL: atomic_max_i8 +; CHECK: lbarx [[DST:[0-9]+]], +; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]] +; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]] +; CHECK-NEXT: ble 0 +} +define i16 @atomic_max_i16() { + top: + %0 = alloca i16, align 2 + %1 = bitcast i16* %0 to i8* + call void @llvm.lifetime.start(i64 2, i8* %1) + store i16 -1, i16* %0, align 2 + %2 = atomicrmw max i16* %0, i16 0 acq_rel + %3 = load atomic i16, i16* %0 acquire, align 8 + call void @llvm.lifetime.end(i64 2, i8* %1) + ret i16 %3 +; CHECK-LABEL: atomic_max_i16 +; CHECK: lharx [[DST:[0-9]+]], +; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]] +; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]] +; CHECK-NEXT: ble 0 +} + +declare void @llvm.lifetime.start(i64, i8*) +declare void @llvm.lifetime.end(i64, i8*) |
