diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP3Instructions.td | 30 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/vop3.s | 10 |
2 files changed, 32 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 99d26eeb402..54a8a07822f 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -106,6 +106,14 @@ def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { let DstRC = RegisterOperand<VReg_64>; } +def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { + // FIXME: Hack to stop printing _e64 + let DstRC = RegisterOperand<VReg_64>; + + let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); + let Asm64 = " $vdst, $sdst, $src0, $src1, $src2"; +} + //===----------------------------------------------------------------------===// // VOP3 Instructions //===----------------------------------------------------------------------===// @@ -229,10 +237,8 @@ def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I3 def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>; let isCommutable = 1 in { -def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3_Profile<VOP_I64_I32_I32_I64>>; - -// XXX - Does this set VCC? -def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3_Profile<VOP_I64_I32_I32_I64>>; +def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; +def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; } // End isCommutable = 1 } // End SubtargetPredicate = isCIVI @@ -386,11 +392,19 @@ multiclass VOP3_Real_ci<bits<9> op> { } } +multiclass VOP3be_Real_ci<bits<9> op> { + def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, + VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> { + let AssemblerPredicates = [isCIOnly]; + let DecoderNamespace = "CI"; + } +} + defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>; defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>; defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>; -defm V_MAD_U64_U32 : VOP3_Real_ci <0x176>; -defm V_MAD_I64_I32 : VOP3_Real_ci <0x177>; +defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>; +defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>; //===----------------------------------------------------------------------===// // VI @@ -411,8 +425,8 @@ multiclass VOP3be_Real_vi<bits<10> op> { } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI" defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>; -defm V_MAD_U64_U32 : VOP3_Real_vi <0x176>; -defm V_MAD_I64_I32 : VOP3_Real_vi <0x177>; +defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; +defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s index baf00658e4b..41ec78ee63f 100644 --- a/llvm/test/MC/AMDGPU/vop3.s +++ b/llvm/test/MC/AMDGPU/vop3.s @@ -390,6 +390,16 @@ v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] // VI: v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] ; encoding: [0x00,0x00,0xe7,0xd1,0x02,0x08,0x02,0x04] // NOSI: error: instruction not supported on this GPU +v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 +// CI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xec,0xd2,0x01,0x00,0x01,0x02] +// VI: v_mad_u64_u32 v[5:6], s[12:13], s1, 0, 0 ; encoding: [0x05,0x0c,0xe8,0xd1,0x01,0x00,0x01,0x02] +// NOSI: error: instruction not supported on this GPU + +v_mad_i64_i32 v[5:6], s[12:13], s1, 0, v[254:255] +// CI: v_mad_i64_i32 v[5:6], s[12:13], s1, 0, v[254:255] ; encoding: [0x05,0x0c,0xee,0xd2,0x01,0x00,0xf9,0x07] +// VI: v_mad_i64_i32 v[5:6], s[12:13], s1, 0, v[254:255] ; encoding: [0x05,0x0c,0xe9,0xd1,0x01,0x00,0xf9,0x07] +// NOSI: error: instruction not supported on this GPU + // // Modifier tests: // |
