diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index de556ed8433..c5f1234fe92 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7562,8 +7562,10 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, const TargetLowering &TLI = DAG.getTargetLoweringInfo(); int FirstLoadedElt = LoadMask.countTrailingZeros(); SDValue EltBase = peekThroughBitcasts(Elts[FirstLoadedElt]); + EVT EltBaseVT = EltBase.getValueType(); + assert(EltBaseVT.getSizeInBits() == EltBaseVT.getStoreSizeInBits() && + "Register/Memory size mismatch"); LoadSDNode *LDBase = Loads[FirstLoadedElt]; - EVT LDBaseVT = EltBase.getValueType(); assert(LDBase && "Did not find base load for merging consecutive loads"); // Consecutive loads can contain UNDEFS but not ZERO elements. @@ -7650,7 +7652,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, } } - unsigned BaseSize = LDBaseVT.getStoreSizeInBits(); + unsigned BaseSize = EltBaseVT.getStoreSizeInBits(); int LoadSize = (1 + LastLoadedElt - FirstLoadedElt) * BaseSize; // If the upper half of a ymm/zmm load is undef then just load the lower half. @@ -7702,7 +7704,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts, continue; bool Match = true; - SmallVector<SDValue, 8> RepeatedLoads(SubElems, DAG.getUNDEF(LDBaseVT)); + SmallVector<SDValue, 8> RepeatedLoads(SubElems, DAG.getUNDEF(EltBaseVT)); for (unsigned i = 0; i != NumElems && Match; ++i) { if (!LoadMask[i]) continue; |
