diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 45 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s | 15 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/fexpa.s | 26 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/ftssel.s | 26 |
6 files changed, 124 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2a8dde28f78..8ebe0cea234 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -135,6 +135,8 @@ let Predicates = [HasSVE] in { defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">; defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">; + defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">; + defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; @@ -199,6 +201,10 @@ let Predicates = [HasSVE] in { def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">; def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">; + def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>; + def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>; + def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>; + def AND_PPzPP : sve_int_pred_log<0b0000, "and">; def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">; def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index cb2cb12788f..a82598c320d 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3959,3 +3959,48 @@ multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> { def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>; def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>; } + + +//===----------------------------------------------------------------------===// +// SVE Integer Misc - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b101100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_bin_cons_misc_0_b<string asm> { + def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>; + def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>; + def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>; +} + +class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn), + asm, "\t$Zd, $Zn", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{7-6}; + let Inst{21} = 0b1; + let Inst{20-16} = opc{5-1}; + let Inst{15-11} = 0b10111; + let Inst{10} = opc{0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +}
\ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s b/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s new file mode 100644 index 00000000000..2269ae0fdfc --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fexpa-diagnostics.s @@ -0,0 +1,15 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid destination or source register. + +fexpa z0.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fexpa z0.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fexpa z0.s, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fexpa z0.s, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE/fexpa.s b/llvm/test/MC/AArch64/SVE/fexpa.s new file mode 100644 index 00000000000..503af1ef80a --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/fexpa.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fexpa z0.h, z31.h +// CHECK-INST: fexpa z0.h, z31.h +// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bb 60 04 <unknown> + +fexpa z0.s, z31.s +// CHECK-INST: fexpa z0.s, z31.s +// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bb a0 04 <unknown> + +fexpa z0.d, z31.d +// CHECK-INST: fexpa z0.d, z31.d +// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bb e0 04 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s b/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s new file mode 100644 index 00000000000..92991246163 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ftssel-diagnostics.s @@ -0,0 +1,6 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +ftssel z0.b, z1.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ftssel z0.b, z1.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE/ftssel.s b/llvm/test/MC/AArch64/SVE/ftssel.s new file mode 100644 index 00000000000..3e9ec71a554 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ftssel.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ftssel z0.h, z1.h, z31.h +// CHECK-INST: ftssel z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xb0,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 b0 7f 04 <unknown> + +ftssel z0.s, z1.s, z31.s +// CHECK-INST: ftssel z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xb0,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 b0 bf 04 <unknown> + +ftssel z0.d, z1.d, z31.d +// CHECK-INST: ftssel z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xb0,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 b0 ff 04 <unknown> |
