diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetLowering.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/include/llvm/Target/TargetLowering.h b/llvm/include/llvm/Target/TargetLowering.h index 052b704ef29..93bdeaaff0e 100644 --- a/llvm/include/llvm/Target/TargetLowering.h +++ b/llvm/include/llvm/Target/TargetLowering.h @@ -1409,15 +1409,12 @@ protected: /// that class natively. void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); - AvailableRegClasses.push_back(std::make_pair(VT, RC)); RegClassForVT[VT.SimpleTy] = RC; } /// Remove all register classes. void clearRegisterClasses() { std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); - - AvailableRegClasses.clear(); } /// \brief Remove all operation actions. @@ -2064,7 +2061,6 @@ private: LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const; private: - std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; /// Targets can specify ISD nodes that they would like PerformDAGCombine /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this |
