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-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp9
-rw-r--r--llvm/test/Transforms/InstCombine/and.ll13
-rw-r--r--llvm/test/Transforms/InstCombine/or.ll16
-rw-r--r--llvm/test/Transforms/InstCombine/xor.ll16
4 files changed, 23 insertions, 31 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 5f16284631e..41395c6bbe6 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -1403,10 +1403,11 @@ Instruction *InstCombiner::visitAnd(BinaryOperator &I) {
return BinaryOperator::CreateAnd(NewCast, C3);
}
}
+ }
+ if (isa<Constant>(Op1))
if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I))
return FoldedLogic;
- }
if (Instruction *DeMorgan = matchDeMorgansLaws(I, Builder))
return DeMorgan;
@@ -2130,10 +2131,11 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) {
return BinaryOperator::CreateXor(Or,
Builder->getInt(C1->getValue() & ~RHS->getValue()));
}
+ }
+ if (isa<Constant>(Op1))
if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I))
return FoldedLogic;
- }
// Given an OR instruction, check to see if this is a bswap.
if (Instruction *BSwap = MatchBSwap(I))
@@ -2593,10 +2595,11 @@ Instruction *InstCombiner::visitXor(BinaryOperator &I) {
}
}
}
+ }
+ if (isa<Constant>(Op1))
if (Instruction *FoldedLogic = foldOpWithConstantIntoOperand(I))
return FoldedLogic;
- }
BinaryOperator *Op1I = dyn_cast<BinaryOperator>(Op1);
if (Op1I) {
diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 34285a2a657..f9cae942b3a 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -517,8 +517,7 @@ define <2 x i32> @test40vec(i1 %C) {
define <2 x i32> @test40vec2(i1 %C) {
; CHECK-LABEL: @test40vec2(
-; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
-; CHECK-NEXT: [[V:%.*]] = and <2 x i32> [[A]], <i32 123, i32 333>
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 104, i32 324>, <2 x i32> <i32 10, i32 12>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
@@ -555,9 +554,8 @@ define <2 x i32> @test41vec(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], <i32 106, i32 106>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 104, i32 104>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
@@ -578,9 +576,8 @@ define <2 x i32> @test41vec2(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], <i32 123, i32 333>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 104, i32 324>, [[ENTRY:%.*]] ], [ <i32 10, i32 12>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index ded9ad8354e..2600136649a 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -714,8 +714,7 @@ define i32 @test49(i1 %C) {
define <2 x i32> @test49vec(i1 %C) {
; CHECK-LABEL: @test49vec(
-; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 896, i32 896>, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[V:%.*]] = or <2 x i32> [[A]], <i32 123, i32 123>
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1019, i32 1019>, <2 x i32> <i32 123, i32 123>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
@@ -725,8 +724,7 @@ define <2 x i32> @test49vec(i1 %C) {
define <2 x i32> @test49vec2(i1 %C) {
; CHECK-LABEL: @test49vec2(
-; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
-; CHECK-NEXT: [[V:%.*]] = or <2 x i32> [[A]], <i32 123, i32 333>
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1019, i32 2509>, <2 x i32> <i32 123, i32 351>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
@@ -763,9 +761,8 @@ define <2 x i32> @test50vec(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], <i32 123, i32 123>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1019, i32 1019>, [[ENTRY:%.*]] ], [ <i32 123, i32 123>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
@@ -786,9 +783,8 @@ define <2 x i32> @test50vec2(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], <i32 123, i32 333>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1019, i32 2509>, [[ENTRY:%.*]] ], [ <i32 123, i32 351>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
diff --git a/llvm/test/Transforms/InstCombine/xor.ll b/llvm/test/Transforms/InstCombine/xor.ll
index 699c1994be1..b5fbfabbda2 100644
--- a/llvm/test/Transforms/InstCombine/xor.ll
+++ b/llvm/test/Transforms/InstCombine/xor.ll
@@ -365,8 +365,7 @@ define i32 @test29(i1 %C) {
define <2 x i32> @test29vec(i1 %C) {
; CHECK-LABEL: @test29vec(
-; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
-; CHECK-NEXT: [[V:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 123>
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 915, i32 915>, <2 x i32> <i32 113, i32 113>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 1000>, <2 x i32> <i32 10, i32 10>
@@ -376,8 +375,7 @@ define <2 x i32> @test29vec(i1 %C) {
define <2 x i32> @test29vec2(i1 %C) {
; CHECK-LABEL: @test29vec2(
-; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
-; CHECK-NEXT: [[V:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 333>
+; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], <2 x i32> <i32 915, i32 2185>, <2 x i32> <i32 113, i32 339>
; CHECK-NEXT: ret <2 x i32> [[V]]
;
%A = select i1 %C, <2 x i32> <i32 1000, i32 2500>, <2 x i32> <i32 10, i32 30>
@@ -414,9 +412,8 @@ define <2 x i32> @test30vec(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 123>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 915, i32 915>, [[ENTRY:%.*]] ], [ <i32 113, i32 113>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
@@ -437,9 +434,8 @@ define <2 x i32> @test30vec2(i1 %which) {
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
-; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
-; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 333>
-; CHECK-NEXT: ret <2 x i32> [[VALUE]]
+; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 915, i32 2185>, [[ENTRY:%.*]] ], [ <i32 113, i32 339>, [[DELAY]] ]
+; CHECK-NEXT: ret <2 x i32> [[A]]
;
entry:
br i1 %which, label %final, label %delay
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