diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll | 6 |
4 files changed, 20 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9db131ce28b..52d483c7b3d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -30209,6 +30209,7 @@ static bool isGRClass(const TargetRegisterClass &RC) { case X86::GR64_NOSPRegClassID: case X86::GR64_NOREX_NOSPRegClassID: case X86::LOW32_ADDR_ACCESSRegClassID: + case X86::LOW32_ADDR_ACCESS_RBPRegClassID: return true; default: return false; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index e32a5fdcdba..cb4170cc623 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -166,7 +166,15 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, // we can still use 64-bit register as long as we know the high bits // are zeros. // Reflect that in the returned register class. - return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass; + if (Is64Bit) { + // When the target also allows 64-bit frame pointer and we do have a + // frame, this is fine to use it for the address accesses as well. + const X86FrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) && TFI->Uses64BitFramePtr + ? &X86::LOW32_ADDR_ACCESS_RBPRegClass + : &X86::LOW32_ADDR_ACCESSRegClass; + } + return &X86::GR32RegClass; case 1: // Normal GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOSPRegClass; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 3c50ac7ce50..797ff4f2e8e 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -427,6 +427,13 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; +// When RBP is used as a base pointer in a 32-bit addresses environement, +// this is also safe to use the full register to access addresses. +// Since RBP will never be spilled, stick to a 32 alignment to save +// on memory consumption. +def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, + (add LOW32_ADDR_ACCESS, RBP)>; + // A class to support the 'A' assembler constraint: EAX then EDX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; diff --git a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll index c476ffd8405..b1f4ca56223 100644 --- a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll +++ b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s -; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s +; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s ; x32 uses %esp, %ebp as stack and frame pointers |
