diff options
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 11 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/cnmips/invalid.s | 4 |
4 files changed, 17 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 1a1682d2a12..42a0c96b876 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3781,6 +3781,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm10_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit unsigned immediate"); + case Match_SImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 10-bit signed immediate"); case Match_UImm16: case Match_UImm16_Relaxed: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 44dc8be156b..fc4d76b518a 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -15,9 +15,6 @@ // Mips Operand, Complex Patterns and Transformations Definitions. //===----------------------------------------------------------------------===// -// Signed Operand -def simm10_64 : Operand<i64>; - // Transformation Function - get Imm - 32. def Subtract32 : SDNodeXForm<imm, [{ return getImm(N, (unsigned)N->getZExtValue() - 32); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 67145c145f0..cb1f705e2f8 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -465,11 +465,13 @@ def UImm16AsmOperandClass : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; def ConstantUImm10AsmOperandClass : ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>; +def ConstantSImm10AsmOperandClass + : ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>; def ConstantSImm7Lsl2AsmOperandClass : AsmOperandClass { let Name = "SImm7Lsl2"; let RenderMethod = "addImmOperands"; let PredicateMethod = "isScaledSImm<7, 2>"; - let SuperClasses = [ConstantUImm10AsmOperandClass]; + let SuperClasses = [ConstantSImm10AsmOperandClass]; let DiagnosticType = "SImm7_Lsl2"; } def ConstantUImm8AsmOperandClass @@ -746,6 +748,13 @@ foreach I = {4, 5, 6} in !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); } +foreach I = {10} in + def simm # I # _64 : Operand<i64> { + let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">"; + let ParserMatchClass = + !cast<AsmOperandClass>("ConstantSImm" # I # "AsmOperandClass"); + } + def simm7_lsl2 : Operand<OtherVT> { let EncoderMethod = "getSImm7Lsl2Encoding"; let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>"; diff --git a/llvm/test/MC/Mips/cnmips/invalid.s b/llvm/test/MC/Mips/cnmips/invalid.s index 2d8e398ed18..f2606d863e5 100644 --- a/llvm/test/MC/Mips/cnmips/invalid.s +++ b/llvm/test/MC/Mips/cnmips/invalid.s @@ -17,3 +17,7 @@ foo: ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate ins $2, $3, 0, -1 # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32 ins $2, $3, 0, 33 # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32 + seqi $2, $3, -1025 # CHECK: :[[@LINE]]:18: error: expected 10-bit signed immediate + seqi $2, $3, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit signed immediate + snei $2, $3, -1025 # CHECK: :[[@LINE]]:18: error: expected 10-bit signed immediate + snei $2, $3, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit signed immediate |
