diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 5 |
2 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 8cdfcfa2acf..d8d45d04eb7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -2976,12 +2976,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { case TargetLowering::Legal: break; case TargetLowering::Custom: Tmp1 = TLI.LowerOperation(Result, DAG); - if (Tmp1.Val) - // FIXME: these braces are correct, but breaks CellSPU codegen. - //{ + if (Tmp1.Val) { Result = Tmp1; break; - //} + } // Fall through if the custom lower can't deal with the operation case TargetLowering::Expand: { MVT VT = Op.getValueType(); diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 2fd72511baa..5f621ed8ec4 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2481,8 +2481,9 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) { DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize)); } } - - return SDValue(); + // These operations (AND, OR, XOR) are legal, they just couldn't be custom + // lowered. Return the operation, rather than a null SDValue. + return Op; } //! Lower i32 multiplication |
