summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--lldb/test/functionalities/register/TestRegisters.py40
1 files changed, 36 insertions, 4 deletions
diff --git a/lldb/test/functionalities/register/TestRegisters.py b/lldb/test/functionalities/register/TestRegisters.py
index 80e82d6c355..551a16baa9b 100644
--- a/lldb/test/functionalities/register/TestRegisters.py
+++ b/lldb/test/functionalities/register/TestRegisters.py
@@ -1,5 +1,5 @@
"""
-Test the 'memory read' command.
+Test the 'register' command.
"""
import os, time
@@ -8,16 +8,24 @@ import unittest2
import lldb
from lldbtest import *
-class MemoryReadTestCase(TestBase):
+class RegisterCommandsTestCase(TestBase):
- mydir = os.path.join("functionalities", "memory", "read")
+ mydir = os.path.join("functionalities", "register")
- @unittest2.skipUnless(os.uname()[4] in ['x86_64'], "requires x86_64")
def test_register_commands(self):
"""Test commands related to registers, in particular xmm registers."""
+ if not self.getArchitecture() in ['i386', 'x86_64']:
+ self.skipTest("This test requires i386 or x86_64 as the architecture for the inferior")
self.buildDefault()
self.register_commands()
+ def test_convenience_registers(self):
+ """Test convenience registers."""
+ if not self.getArchitecture() in ['x86_64']:
+ self.skipTest("This test requires x86_64 as the architecture for the inferior")
+ self.buildDefault()
+ self.convenience_registers()
+
def register_commands(self):
"""Test commands related to registers, in particular xmm registers."""
exe = os.path.join(os.getcwd(), "a.out")
@@ -47,6 +55,30 @@ class MemoryReadTestCase(TestBase):
self.expect("expr (unsigned int)$xmm0[0]",
substrs = ['unsigned int'])
+ def convenience_registers(self):
+ """Test convenience registers."""
+ exe = os.path.join(os.getcwd(), "a.out")
+ self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+ # Break in main().
+ self.expect("breakpoint set -n main",
+ BREAKPOINT_CREATED,
+ startstr = "Breakpoint created: 1: name = 'main'")
+
+ self.runCmd("run", RUN_SUCCEEDED)
+
+ # The stop reason of the thread should be breakpoint.
+ self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
+ substrs = ['stopped', 'stop reason = breakpoint'])
+
+ # Test reading of rax and eax.
+ self.runCmd("register read rax eax")
+
+ # No write rax with a unique bit pattern and test that eax indeed represents the lower half of rax.
+ self.runCmd("register write rax 0x1234567887654321")
+ self.expect("expr -- ($rax & 0xffffffff) == $eax",
+ substrs = ['true'])
+
if __name__ == '__main__':
import atexit
OpenPOWER on IntegriCloud