diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetOptions.h | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocBasic.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/TargetMachine.cpp | 8 |
4 files changed, 7 insertions, 14 deletions
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index cb22b1826d9..3f42bbe16a0 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -34,10 +34,6 @@ namespace llvm { /// wth earlier copy coalescing. extern bool StrongPHIElim; - /// EnableMachineSched - temporary flag to enable the machine scheduling pass - /// until we complete the register allocation pass configuration cleanup. - extern bool EnableMachineSched; - class TargetOptions { public: TargetOptions() diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index cb92513d8ec..dbddf722d16 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -149,8 +149,6 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { if (StrongPHIElim) AU.addRequiredID(StrongPHIEliminationID); AU.addRequiredTransitiveID(RegisterCoalescerPassID); - if (EnableMachineSched) - AU.addRequiredID(MachineSchedulerPassID); AU.addRequired<CalculateSpillWeights>(); AU.addRequired<LiveStacks>(); AU.addPreserved<LiveStacks>(); diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index bced80ca540..16832ceaf3d 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -51,6 +51,13 @@ STATISTIC(NumGlobalSplits, "Number of split global live ranges"); STATISTIC(NumLocalSplits, "Number of split local live ranges"); STATISTIC(NumEvicted, "Number of interferences evicted"); +/// EnableMachineSched - temporary flag to enable the machine scheduling pass +/// until we complete the register allocation pass configuration cleanup. +static cl::opt<bool> +EnableMachineSched("enable-misched", + cl::desc("Enable the machine instruction scheduling pass."), + cl::init(false), cl::Hidden); + static cl::opt<SplitEditor::ComplementSpillMode> SplitSpillMode("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index 90042dc1d52..19819b886c1 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -37,14 +37,6 @@ FunctionSections("ffunction-sections", cl::desc("Emit functions into separate sections"), cl::init(false)); -/// EnableMachineSched - temporary flag to enable the machine scheduling pass -/// until we complete the register allocation pass configuration cleanup. -static cl::opt<bool, true> -MachineSchedOpt("enable-misched", - cl::desc("Enable the machine instruction scheduling pass."), - cl::location(EnableMachineSched), - cl::init(false), cl::Hidden); - //--------------------------------------------------------------------------- // TargetMachine Class // |
