diff options
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/cfg-stackify.ll | 3 |
2 files changed, 3 insertions, 10 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp index 201c5ab0bc1..af53f3db967 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp @@ -106,16 +106,10 @@ bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { // If we weren't able to invert the condition in place. Insert an // expression to invert it. if (!Inverted) { - unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); - MFI.stackifyVReg(ZeroReg); - BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), - ZeroReg) - .addImm(0); unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass); MFI.stackifyVReg(Tmp); - BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp) - .addReg(Cond) - .addReg(ZeroReg); + BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp) + .addReg(Cond); Cond = Tmp; Inverted = true; } diff --git a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll index b29cd8860a2..ff945706778 100644 --- a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll +++ b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll @@ -1261,8 +1261,7 @@ bb50: ; OPT: block ; OPT: block ; OPT-NEXT: i32.const $push -; OPT-NEXT: i32.const $push -; OPT-NEXT: i32.eq $push{{.*}}=, $pop{{.*}}, $pop{{.*}}{{$}} +; OPT-NEXT: i32.eqz $push{{.*}}=, $pop{{.*}}{{$}} ; OPT-NEXT: br_if 0, $pop{{.*}}{{$}} ; OPT-NEXT: call test15_callee1@FUNCTION{{$}} ; OPT-NEXT: br 1{{$}} |
