diff options
7 files changed, 7 insertions, 7 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index ae0055ce691..eacd13582dc 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -218,7 +218,7 @@ enum { /// - InsnID - Instruction ID to modify /// - RegNum - The register to add GIR_AddRegister, - /// Add a a temporary register to the specified instruction + /// Add a temporary register to the specified instruction /// - InsnID - Instruction ID to modify /// - TempRegID - The temporary register ID to add GIR_AddTempRegister, diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index e89f0f855ed..d06d96be542 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -218,7 +218,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { unsigned Size = TRI->getRegSizeInBits(*RC); Result.Named.LGKM = Size > 32 ? 2 : 1; } else { - // s_dcache_inv etc. do not have a a destination register. Assume we + // s_dcache_inv etc. do not have a destination register. Assume we // want a wait on these. // XXX - What is the right value? Result.Named.LGKM = 1; diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 02c6eb925ca..95481e042b9 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -358,7 +358,7 @@ int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) { int ISD = TLI->InstructionOpcodeToISD(Opcode); - // On NEON a a vector select gets lowered to vbsl. + // On NEON a vector select gets lowered to vbsl. if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) { // Lowering of some vector selects is currently far from perfect. static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = { diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 65a2fc35b11..e8c43de8529 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1914,7 +1914,7 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF, if (OptimizeSpillSlots && !isOptNone(MF)) optimizeSpillSlots(MF, NewRegs); - // We need to reserve a a spill slot if scavenging could potentially require + // We need to reserve a spill slot if scavenging could potentially require // spilling a scavenged register. if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) { MachineFrameInfo &MFI = MF.getFrameInfo(); diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index f36a4317b1b..5bcddb704a8 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3885,7 +3885,7 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, // This is accomplished by using a BNEZ with the result of the SLT. // // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT - // and BLE with BGT), so we change the BNEZ into a a BEQZ. + // and BLE with BGT), so we change the BNEZ into a BEQZ. // Because only BGE and BLE branch on equality, we can use the // AcceptsEquality variable to decide when to emit the BEQZ. // Note that the order of the SLT arguments doesn't change between diff --git a/llvm/test/tools/llvm-xray/X86/extract-all-sledtypes.txt b/llvm/test/tools/llvm-xray/X86/extract-all-sledtypes.txt index a4ac925cbd6..f9942d190c8 100644 --- a/llvm/test/tools/llvm-xray/X86/extract-all-sledtypes.txt +++ b/llvm/test/tools/llvm-xray/X86/extract-all-sledtypes.txt @@ -1,5 +1,5 @@ # Test that we can extract all the sled types we know about. This is built with -# a a file with functions always instrumented, and using the built-ins and +# a file with functions always instrumented, and using the built-ins and # intrinsics supported by clang. Those are built with: # # clang++ -c all-sleds.cc -o all-sleds.o -fpic -std=c++11 -fxray-instrument diff --git a/llvm/tools/llvm-readobj/COFFDumper.cpp b/llvm/tools/llvm-readobj/COFFDumper.cpp index 40334802d8e..f40e0d9c9a3 100644 --- a/llvm/tools/llvm-readobj/COFFDumper.cpp +++ b/llvm/tools/llvm-readobj/COFFDumper.cpp @@ -244,7 +244,7 @@ std::error_code createCOFFDumper(const object::ObjectFile *Obj, } // namespace llvm -// Given a a section and an offset into this section the function returns the +// Given a section and an offset into this section the function returns the // symbol used for the relocation at the offset. std::error_code COFFDumper::resolveSymbol(const coff_section *Section, uint64_t Offset, SymbolRef &Sym) { |
