diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 37 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 15 |
3 files changed, 41 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 3b1a9d54f44..0adf1c4ce1f 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1657,8 +1657,8 @@ SIScheduleDAGMI::SIScheduleDAGMI(MachineSchedContext *C) : SITII = static_cast<const SIInstrInfo*>(TII); SITRI = static_cast<const SIRegisterInfo*>(TRI); - VGPRSetID = SITRI->getVGPR32PressureSet(); - SGPRSetID = SITRI->getSGPR32PressureSet(); + VGPRSetID = SITRI->getVGPRPressureSet(); + SGPRSetID = SITRI->getSGPRPressureSet(); } SIScheduleDAGMI::~SIScheduleDAGMI() { diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index a1c83f5d736..90eda52a8c1 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -95,19 +95,38 @@ SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo(), VGPRPressureSets(getNumRegPressureSets()) { unsigned NumRegPressureSets = getNumRegPressureSets(); - SGPR32SetID = NumRegPressureSets; - VGPR32SetID = NumRegPressureSets; - for (unsigned i = 0; i < NumRegPressureSets; ++i) { - if (strncmp("SGPR_32", getRegPressureSetName(i), 7) == 0) - SGPR32SetID = i; - else if (strncmp("VGPR_32", getRegPressureSetName(i), 7) == 0) - VGPR32SetID = i; + SGPRSetID = NumRegPressureSets; + VGPRSetID = NumRegPressureSets; + for (unsigned i = 0; i < NumRegPressureSets; ++i) { classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets); classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); } - assert(SGPR32SetID < NumRegPressureSets && - VGPR32SetID < NumRegPressureSets); + + // Determine the number of reg units for each pressure set. + std::vector<unsigned> PressureSetRegUnits(NumRegPressureSets, 0); + for (unsigned i = 0, e = getNumRegUnits(); i != e; ++i) { + const int *PSets = getRegUnitPressureSets(i); + for (unsigned j = 0; PSets[j] != -1; ++j) { + PressureSetRegUnits[PSets[j]]++; + } + } + + unsigned VGPRMax = 0, SGPRMax = 0; + for (unsigned i = 0; i < NumRegPressureSets; ++i) { + if (isVGPRPressureSet(i) && PressureSetRegUnits[i] > VGPRMax) { + VGPRSetID = i; + VGPRMax = PressureSetRegUnits[i]; + continue; + } + if (isSGPRPressureSet(i) && PressureSetRegUnits[i] > SGPRMax) { + SGPRSetID = i; + SGPRMax = PressureSetRegUnits[i]; + } + } + + assert(SGPRSetID < NumRegPressureSets && + VGPRSetID < NumRegPressureSets); } void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 087631db684..b0e852e6127 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -25,8 +25,8 @@ class MachineRegisterInfo; struct SIRegisterInfo final : public AMDGPURegisterInfo { private: - unsigned SGPR32SetID; - unsigned VGPR32SetID; + unsigned SGPRSetID; + unsigned VGPRSetID; BitVector SGPRPressureSets; BitVector VGPRPressureSets; @@ -182,11 +182,18 @@ public: const TargetRegisterClass *RC, const MachineFunction &MF) const; - unsigned getSGPR32PressureSet() const { return SGPR32SetID; }; - unsigned getVGPR32PressureSet() const { return VGPR32SetID; }; + unsigned getSGPRPressureSet() const { return SGPRSetID; }; + unsigned getVGPRPressureSet() const { return VGPRSetID; }; bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const; + bool isSGPRPressureSet(unsigned SetID) const { + return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID); + } + bool isVGPRPressureSet(unsigned SetID) const { + return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID); + } + private: void buildScratchLoadStore(MachineBasicBlock::iterator MI, unsigned LoadStoreOp, const MachineOperand *SrcDst, |
