diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 18 |
2 files changed, 11 insertions, 9 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def index bbff85f906e..88dac21bab3 100644 --- a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -101,7 +101,7 @@ RegisterBankInfo::ValueMapping ValMappings[] { /// /// \pre \p RBIdx != PartialMappingIdx::None const RegisterBankInfo::ValueMapping * -getValueMappingIdx(PartialMappingIdx RBIdx, unsigned Size) { +getValueMapping(PartialMappingIdx RBIdx, unsigned Size) { assert(RBIdx != PartialMappingIdx::None && "No mapping needed for that"); unsigned ValMappingIdx = First3OpsIdx + (RBIdx + getRegBankBaseIdxOffset(Size)) * diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 35b229a6a0b..3efa0dc53aa 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -246,12 +246,12 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings( if (MI.getNumOperands() != 3) break; InstructionMappings AltMappings; - InstructionMapping GPRMapping(/*ID*/ 1, /*Cost*/ 1, - getValueMappingIdx(AArch64::FirstGPR, Size), - /*NumOperands*/ 3); - InstructionMapping FPRMapping(/*ID*/ 2, /*Cost*/ 1, - getValueMappingIdx(AArch64::FirstFPR, Size), - /*NumOperands*/ 3); + InstructionMapping GPRMapping( + /*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstGPR, Size), + /*NumOperands*/ 3); + InstructionMapping FPRMapping( + /*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstFPR, Size), + /*NumOperands*/ 3); AltMappings.emplace_back(std::move(GPRMapping)); AltMappings.emplace_back(std::move(FPRMapping)); @@ -352,7 +352,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { IsFPR ? AArch64::FirstFPR : AArch64::FirstGPR; return InstructionMapping{DefaultMappingID, 1, - getValueMappingIdx(RBIdx, Size), NumOperands}; + AArch64::getValueMapping(RBIdx, Size), + NumOperands}; } default: break; @@ -405,7 +406,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands); for (unsigned Idx = 0; Idx < NumOperands; ++Idx) if (MI.getOperand(Idx).isReg()) - OpdsMapping[Idx] = getValueMappingIdx(OpRegBankIdx[Idx], OpSize[Idx]); + OpdsMapping[Idx] = + AArch64::getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]); Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping)); return Mapping; |
