diff options
| -rw-r--r-- | llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s | 99 | ||||
| -rw-r--r-- | llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s | 105 |
2 files changed, 202 insertions, 2 deletions
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s b/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s index d077a07ef41..00b03afbf0d 100644 --- a/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -scheduler-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s # LLVM-MCA-BEGIN movb (%rax), %spl @@ -76,6 +76,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movb (%rdx), %sil # CHECK-NEXT: 1 5 0.50 * movb (%rbx), %dil +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -175,6 +189,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movw (%rdx), %si # CHECK-NEXT: 1 5 0.50 * movw (%rbx), %di +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -274,6 +302,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movl (%rdx), %esi # CHECK-NEXT: 1 5 0.50 * movl (%rbx), %edi +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -373,6 +415,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movq (%rdx), %rsi # CHECK-NEXT: 1 5 0.50 * movq (%rbx), %rdi +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -472,6 +528,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movd (%rdx), %mm2 # CHECK-NEXT: 1 5 0.50 * movd (%rbx), %mm3 +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -571,6 +641,20 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 1 5 0.50 * movaps (%rdx), %xmm2 # CHECK-NEXT: 1 5 0.50 * movaps (%rbx), %xmm3 +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 161 (77.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (12.6%) +# CHECK-NEXT: 2, 162 (78.3%) +# CHECK-NEXT: 4, 19 (9.2%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) @@ -670,6 +754,19 @@ vmovaps (%rbx), %ymm3 # CHECK-NEXT: 2 5 0.50 * vmovaps (%rdx), %ymm2 # CHECK-NEXT: 2 5 0.50 * vmovaps (%rbx), %ymm3 +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 7 (3.4%) +# CHECK-NEXT: 4, 200 (96.6%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 7 (3.4%) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s b/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s index 0a55e825d0c..76892986055 100644 --- a/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -scheduler-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s # LLVM-MCA-BEGIN movb %spl, (%rax) @@ -76,6 +76,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 1 1.00 * movb %sil, (%rdx) # CHECK-NEXT: 1 1 1.00 * movb %dil, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 369 (91.6%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (6.5%) +# CHECK-NEXT: 1, 369 (91.6%) +# CHECK-NEXT: 3, 1 (0.2%) +# CHECK-NEXT: 4, 7 (1.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) @@ -175,6 +190,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 1 1.00 * movw %si, (%rdx) # CHECK-NEXT: 1 1 1.00 * movw %di, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 369 (91.6%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (6.5%) +# CHECK-NEXT: 1, 369 (91.6%) +# CHECK-NEXT: 3, 1 (0.2%) +# CHECK-NEXT: 4, 7 (1.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) @@ -274,6 +304,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 1 1.00 * movl %esi, (%rdx) # CHECK-NEXT: 1 1 1.00 * movl %edi, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 369 (91.6%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (6.5%) +# CHECK-NEXT: 1, 369 (91.6%) +# CHECK-NEXT: 3, 1 (0.2%) +# CHECK-NEXT: 4, 7 (1.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) @@ -373,6 +418,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 1 1.00 * movq %rsi, (%rdx) # CHECK-NEXT: 1 1 1.00 * movq %rdi, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 369 (91.6%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (6.5%) +# CHECK-NEXT: 1, 369 (91.6%) +# CHECK-NEXT: 3, 1 (0.2%) +# CHECK-NEXT: 4, 7 (1.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) @@ -472,6 +532,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 2 1.00 * U movd %mm2, (%rdx) # CHECK-NEXT: 1 2 1.00 * U movd %mm3, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 745 (92.8%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 423 (52.7%) +# CHECK-NEXT: 1, 373 (46.5%) +# CHECK-NEXT: 3, 1 (0.1%) +# CHECK-NEXT: 4, 6 (0.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 403 (50.2%) @@ -572,6 +647,21 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 1 1 1.00 * movaps %xmm2, (%rdx) # CHECK-NEXT: 1 1 1.00 * movaps %xmm3, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 369 (91.6%) +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 26 (6.5%) +# CHECK-NEXT: 1, 369 (91.6%) +# CHECK-NEXT: 3, 1 (0.2%) +# CHECK-NEXT: 4, 7 (1.7%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) @@ -671,6 +761,19 @@ vmovaps %ymm3, (%rbx) # CHECK-NEXT: 4 1 1.00 * vmovaps %ymm2, (%rdx) # CHECK-NEXT: 4 1 1.00 * vmovaps %ymm3, (%rbx) +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 3 (0.7%) +# CHECK-NEXT: 4, 400 (99.3%) + # CHECK: Schedulers - number of cycles where we saw N instructions issued: # CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: 0, 3 (0.7%) |
