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-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFormats.td118
1 files changed, 59 insertions, 59 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 0e63f37bd7e..8c990ecc03e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -2469,7 +2469,7 @@ class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes, bits<4> type = 0>
: InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
mnemonic#"\t$V1, $XBD2",
- [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
+ [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> {
let M3 = type;
let mayStore = 1;
let AccessBytes = bytes;
@@ -2844,7 +2844,7 @@ class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, Immediate imm, bits<4> type = 0>
: InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
mnemonic#"\t$V1, $I2",
- [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
+ [(set (tr.vt tr.op:$V1), (operator imm:$I2))]> {
let M3 = type;
}
@@ -2857,7 +2857,7 @@ class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<4> m5 = 0>
: InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
mnemonic#"\t$V1, $V2",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> {
let M3 = type;
let M4 = m4;
let M5 = m5;
@@ -2913,7 +2913,7 @@ class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes, bits<4> type = 0>
: InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
mnemonic#"\t$V1, $XBD2",
- [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
+ [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> {
let M3 = type;
let mayLoad = 1;
let AccessBytes = bytes;
@@ -3387,7 +3387,7 @@ class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<4> type>
: InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
mnemonic#"\t$V1, $I2, $I3",
- [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
+ [(set (tr.vt tr.op:$V1), (operator imm32zx8:$I2, imm32zx8:$I3))]> {
let M4 = type;
}
@@ -3400,8 +3400,8 @@ class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<4> type>
: InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
mnemonic#"\t$V1, $V3, $I2",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
- imm32zx16:$I2)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
+ imm32zx16:$I2))]> {
let M4 = type;
}
@@ -3414,8 +3414,8 @@ class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
: InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
mnemonic#"\t$V1, $V2, $I3",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- imm32zx12:$I3)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ imm32zx12:$I3))]> {
let M4 = type;
let M5 = m5;
}
@@ -3434,8 +3434,8 @@ class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
: InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
mnemonic#"\t$V1, $V2, $M5",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- imm32zx12:$M5)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ imm32zx12:$M5))]> {
let M3 = type;
let M4 = m4;
}
@@ -3450,8 +3450,8 @@ class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<4> modifier = 0>
: InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
mnemonic#"\t$V1, $V2, $V3",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3))))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3)))]> {
let M4 = type;
let M5 = modifier;
}
@@ -3509,8 +3509,8 @@ class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bits<4> m6 = 0>
: InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
mnemonic#"\t$V1, $V2, $V3",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3))))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3)))]> {
let M4 = type;
let M5 = m5;
let M6 = m6;
@@ -3556,7 +3556,7 @@ class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr>
: InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
mnemonic#"\t$V1, $R2, $R3",
- [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
+ [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>;
class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
@@ -3566,8 +3566,8 @@ class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, bits<4> type>
: InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
mnemonic#"\t$V1, $V3, $BD2",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
- shift12only:$BD2)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
+ shift12only:$BD2))]> {
let M4 = type;
}
@@ -3612,8 +3612,8 @@ class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<5> bytes>
: InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
mnemonic#"\t$V1, $XBD2, $M3",
- [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
- imm32zx4:$M3)))]> {
+ [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2,
+ imm32zx4:$M3))]> {
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4099,8 +4099,8 @@ class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
: InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
mnemonic#"\t$V1, $I2, $M3",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
- imm:$I2, index:$M3)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
+ imm:$I2, index:$M3))]> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
}
@@ -4110,9 +4110,9 @@ class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRId<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
mnemonic#"\t$V1, $V2, $V3, $I4",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- imm32zx8:$I4)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ imm32zx8:$I4))]> {
let M5 = type;
}
@@ -4126,9 +4126,9 @@ class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRRa<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
mnemonic#"\t$V1, $V2, $M4, $M5",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- imm32zx4:$M4,
- imm32zx4:$M5)))],
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ imm32zx4:$M4,
+ imm32zx4:$M5))],
m4or> {
let M3 = type;
}
@@ -4144,9 +4144,9 @@ class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRRb<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
mnemonic#"\t$V1, $V2, $V3, $M5",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- m5mask:$M5)))],
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ m5mask:$M5))],
m5or> {
let M4 = type;
}
@@ -4186,9 +4186,9 @@ class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRRc<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
mnemonic#"\t$V1, $V2, $V3, $M4",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- imm32zx4:$M4)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ imm32zx4:$M4))]> {
let M5 = 0;
let M6 = 0;
}
@@ -4199,9 +4199,9 @@ class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
: InstVRRc<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
mnemonic#"\t$V1, $V2, $V3, $M6",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- imm32zx4:$M6)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ imm32zx4:$M6))]> {
let M4 = type;
let M5 = m5;
}
@@ -4217,9 +4217,9 @@ class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRRd<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
mnemonic#"\t$V1, $V2, $V3, $V4",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- (tr1.vt tr1.op:$V4))))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ (tr1.vt tr1.op:$V4)))]> {
let M5 = type;
let M6 = 0;
}
@@ -4236,9 +4236,9 @@ class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRRe<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
mnemonic#"\t$V1, $V2, $V3, $V4",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- (tr1.vt tr1.op:$V4))))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ (tr1.vt tr1.op:$V4)))]> {
let M5 = m5;
let M6 = type;
}
@@ -4253,9 +4253,9 @@ class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRSb<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
mnemonic#"\t$V1, $R3, $BD2",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
- cls:$R3,
- shift12only:$BD2)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
+ cls:$R3,
+ shift12only:$BD2))]> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
let M4 = type;
@@ -4285,9 +4285,9 @@ class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
: InstVRX<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
mnemonic#"\t$V1, $XBD2, $M3",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
- bdxaddr12only:$XBD2,
- index:$M3)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
+ bdxaddr12only:$XBD2,
+ index:$M3))]> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
let mayLoad = 1;
@@ -4299,10 +4299,10 @@ class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operato
: InstVRId<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
mnemonic#"\t$V1, $V2, $V3, $I4",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
- (tr2.vt tr2.op:$V2),
- (tr2.vt tr2.op:$V3),
- imm32zx8:$I4)))]> {
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
+ (tr2.vt tr2.op:$V2),
+ (tr2.vt tr2.op:$V3),
+ imm32zx8:$I4))]> {
let Constraints = "$V1 = $V1src";
let DisableEncoding = "$V1src";
let M5 = type;
@@ -4336,10 +4336,10 @@ class QuaternaryVRRd<string mnemonic, bits<16> opcode,
: InstVRRd<opcode, (outs tr1.op:$V1),
(ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
- (tr3.vt tr3.op:$V3),
- (tr4.vt tr4.op:$V4),
- m6mask:$M6)))],
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
+ (tr3.vt tr3.op:$V3),
+ (tr4.vt tr4.op:$V4),
+ m6mask:$M6))],
m6or> {
let M5 = type;
}
@@ -4814,13 +4814,13 @@ class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
// An alias of a UnaryVRR*, but with different register sizes.
class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
: Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
- [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
+ [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;
// An alias of a UnaryVRX, but with different register sizes.
class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
AddressingMode mode = bdxaddr12only>
: Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
- [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
+ [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>;
// An alias of a StoreVRX, but with different register sizes.
class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
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