diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 7 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rvd-aliases-valid.s | 7 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rvf-aliases-valid.s | 7 |
4 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index b308cb990a0..06b834d55ad 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -185,6 +185,13 @@ let Predicates = [HasStdExtD] in { def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; + +// fgt.d/fge.d are recognised by the GNU assembler but the canonical +// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. +def : InstAlias<"fgt.d $rd, $rs, $rt", + (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; +def : InstAlias<"fge.d $rd, $rs, $rt", + (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; } // Predicates = [HasStdExtD] //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 6121dea277c..12b1d9a857f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -200,6 +200,13 @@ def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; +// fgt.s/fge.s are recognised by the GNU assembler but the canonical +// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. +def : InstAlias<"fgt.s $rd, $rs, $rt", + (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; +def : InstAlias<"fge.s $rd, $rs, $rt", + (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; + // The following csr instructions actually alias instructions from the base ISA. // However, it only makes sense to support them when the F extension is enabled. // CSR Addresses: 0x003 == fcsr, 0x002 == frm, 0x001 == fflags diff --git a/llvm/test/MC/RISCV/rvd-aliases-valid.s b/llvm/test/MC/RISCV/rvd-aliases-valid.s index 29601048ec9..173d998b76a 100644 --- a/llvm/test/MC/RISCV/rvd-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvd-aliases-valid.s @@ -36,6 +36,13 @@ fabs.d f1, f2 # CHECK-ALIAS: fneg.d ft2, ft3 fneg.d f2, f3 +# CHECK-INST: flt.d tp, ft6, ft5 +# CHECK-ALIAS: flt.d tp, ft6, ft5 +fgt.d x4, f5, f6 +# CHECK-INST: fle.d t2, fs1, fs0 +# CHECK-ALIAS: fle.d t2, fs1, fs0 +fge.d x7, f8, f9 + ##===----------------------------------------------------------------------===## ## Aliases which omit the rounding mode. ##===----------------------------------------------------------------------===## diff --git a/llvm/test/MC/RISCV/rvf-aliases-valid.s b/llvm/test/MC/RISCV/rvf-aliases-valid.s index d306eb77e09..c6da9b39909 100644 --- a/llvm/test/MC/RISCV/rvf-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvf-aliases-valid.s @@ -36,6 +36,13 @@ fabs.s f1, f2 # CHECK-ALIAS: fneg.s ft2, ft3 fneg.s f2, f3 +# CHECK-INST: flt.s tp, ft6, ft5 +# CHECK-ALIAS: flt.s tp, ft6, ft5 +fgt.s x4, f5, f6 +# CHECK-INST: fle.s t2, fs1, fs0 +# CHECK-ALIAS: fle.s t2, fs1, fs0 +fge.s x7, f8, f9 + # The following instructions actually alias instructions from the base ISA. # However, it only makes sense to support them when the F extension is enabled. # CHECK-INST: csrrs t0, 3, zero |
