diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 16 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips-dsp/valid.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips-dspr2/valid.s | 8 |
6 files changed, 50 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td index 938b4b07c06..7f8f88b9552 100644 --- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -102,6 +102,14 @@ class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>; class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>; class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>; class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>; +class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>; +class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>; +class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>; +class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>; +class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>; +class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>; +class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>; +class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>; // Instruction desc. class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, @@ -327,6 +335,10 @@ def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC; def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC; def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC; def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC; +def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC; +def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC; +def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC; +def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; @@ -360,3 +372,9 @@ def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2; def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2; def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2; def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; +def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2; +def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC, + ISA_DSPR2; +def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC, + ISA_DSPR2; +def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2; diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index 4afa301e78f..9a7c7944ca1 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -1151,12 +1151,12 @@ def MTHI_DSP : MTHI_ENC, MTHI_DESC; def MTLO_DSP : MTLO_ENC, MTLO_DESC; def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; -def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; -def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; +def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; +def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; -def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; +def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; -def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; +def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC; def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC; def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC; @@ -1232,13 +1232,13 @@ def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC; -def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; +def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC; def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC; -def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; -def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; -def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; +def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC; +def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; +def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt index 0f4b3c6797e..93a7f966a56 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -63,3 +63,7 @@ 0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5 0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5 0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5 +0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6 +0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6 +0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6 +0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6 diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt index e6a05531a39..c1d076365b8 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt @@ -90,3 +90,11 @@ 0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5 0x00 0xa4 0x1b 0x4d # CHECK: subuh.qb $3, $4, $5 0x00 0xa4 0x1f 0x4d # CHECK: subuh_r.qb $3, $4, $5 +0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6 +0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6 +0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6 +0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6 +0x00 0xc4 0x44 0xbc # CHECK: dps.w.ph $ac1, $4, $6 +0x00 0xc4 0x66 0xbc # CHECK: dpsqx_s.w.ph $ac1, $4, $6 +0x00 0xc4 0x76 0xbc # CHECK: dpsqx_sa.w.ph $ac1, $4, $6 +0x00 0xc4 0x54 0xbc # CHECK: dpsx.w.ph $ac1, $4, $6 diff --git a/llvm/test/MC/Mips/micromips-dsp/valid.s b/llvm/test/MC/Mips/micromips-dsp/valid.s index 1621c531584..fb13144b25e 100644 --- a/llvm/test/MC/Mips/micromips-dsp/valid.s +++ b/llvm/test/MC/Mips/micromips-dsp/valid.s @@ -64,3 +64,7 @@ subq_s.w $3, $4, $5 # CHECK: subq_s.w $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x45] subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd] subu_s.qb $3, $4, $5 # CHECK: subu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0xcd] + dpsq_s.w.ph $ac1, $4, $6 # CHECK: dpsq_s.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x46,0xbc] + dpsq_sa.l.w $ac1, $4, $6 # CHECK: dpsq_sa.l.w $ac1, $4, $6 # encoding: [0x00,0xc4,0x56,0xbc] + dpsu.h.qbl $ac1, $4, $6 # CHECK: dpsu.h.qbl $ac1, $4, $6 # encoding: [0x00,0xc4,0x64,0xbc] + dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc] diff --git a/llvm/test/MC/Mips/micromips-dspr2/valid.s b/llvm/test/MC/Mips/micromips-dspr2/valid.s index 5dd93c50dfe..8978c54c8ef 100644 --- a/llvm/test/MC/Mips/micromips-dspr2/valid.s +++ b/llvm/test/MC/Mips/micromips-dspr2/valid.s @@ -91,3 +91,11 @@ subu_s.qb $3, $4, $5 # CHECK: subu_s.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1e,0xcd] subuh.qb $3, $4, $5 # CHECK: subuh.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x4d] subuh_r.qb $3, $4, $5 # CHECK: subuh_r.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1f,0x4d] + dpsq_s.w.ph $ac1, $4, $6 # CHECK: dpsq_s.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x46,0xbc] + dpsq_sa.l.w $ac1, $4, $6 # CHECK: dpsq_sa.l.w $ac1, $4, $6 # encoding: [0x00,0xc4,0x56,0xbc] + dpsu.h.qbl $ac1, $4, $6 # CHECK: dpsu.h.qbl $ac1, $4, $6 # encoding: [0x00,0xc4,0x64,0xbc] + dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc] + dps.w.ph $ac1, $4, $6 # CHECK: dps.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x44,0xbc] + dpsqx_s.w.ph $ac1, $4, $6 # CHECK: dpsqx_s.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x66,0xbc] + dpsqx_sa.w.ph $ac1, $4, $6 # CHECK: dpsqx_sa.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x76,0xbc] + dpsx.w.ph $ac1, $4, $6 # CHECK: dpsx.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x54,0xbc] |
