diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPeephole.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll | 27 |
2 files changed, 31 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index b064decc5c7..8d1ddeb3aaf 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -250,6 +250,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { // Change the 1st operand and, flip the opcode. MI.getOperand(0).setReg(PeepholeSrc); + MRI->clearKillFlags(PeepholeSrc); int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode()); MI.setDesc(QII->get(NewOp)); Done = true; @@ -280,6 +281,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { unsigned PSrc = MI.getOperand(PR).getReg(); if (unsigned POrig = PeepholeMap.lookup(PSrc)) { MI.getOperand(PR).setReg(POrig); + MRI->clearKillFlags(POrig); MI.setDesc(QII->get(NewOp)); // Swap operands S1 and S2. MachineOperand Op1 = MI.getOperand(S1); @@ -304,6 +306,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) { if (Src.isReg()) { Dst.setReg(Src.getReg()); Dst.setSubReg(Src.getSubReg()); + MRI->clearKillFlags(Src.getReg()); } else if (Src.isImm()) { Dst.ChangeToImmediate(Src.getImm()); } else { @@ -316,7 +319,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) { Dst.setImm(Src.getImm()); } else if (Src.isReg()) { Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(), - Src.isKill(), Src.isDead(), Src.isUndef(), + false, Src.isDead(), Src.isUndef(), Src.isDebug()); Dst.setSubReg(Src.getSubReg()); } else { diff --git a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll new file mode 100644 index 00000000000..03de1532352 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; CHECK: memw + +; Check that the testcase compiles without errors. + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @fred() #0 { +entry: + br label %for.cond + +for.cond: ; preds = %entry + %0 = load i32, i32* undef, align 4 + %mul = mul nsw i32 2, %0 + %cmp = icmp slt i32 undef, %mul + br i1 %cmp, label %for.body, label %for.end13 + +for.body: ; preds = %for.cond + unreachable + +for.end13: ; preds = %for.cond + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } + |
