diff options
26 files changed, 515 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2076e596700..e256f5daf15 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -342,7 +342,7 @@ let Predicates = [HasSVE] in { defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>; defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>; - // ST{2,3,4}{B,H,W,D} with immediate + // ST(2|3|4) structured stores (register + immediate) defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>; defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>; defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4s4>; @@ -356,6 +356,20 @@ let Predicates = [HasSVE] in { defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>; defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>; + // ST(2|3|4) structured stores (register + register) + def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>; + def ST3B : sve_mem_est_ss<0b00, 0b10, ZZZ_b, "st3b", GPR64NoXZRshifted8>; + def ST4B : sve_mem_est_ss<0b00, 0b11, ZZZZ_b, "st4b", GPR64NoXZRshifted8>; + def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>; + def ST3H : sve_mem_est_ss<0b01, 0b10, ZZZ_h, "st3h", GPR64NoXZRshifted16>; + def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>; + def ST2W : sve_mem_est_ss<0b10, 0b01, ZZ_s, "st2w", GPR64NoXZRshifted32>; + def ST3W : sve_mem_est_ss<0b10, 0b10, ZZZ_s, "st3w", GPR64NoXZRshifted32>; + def ST4W : sve_mem_est_ss<0b10, 0b11, ZZZZ_s, "st4w", GPR64NoXZRshifted32>; + def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>; + def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>; + def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>; + // Non-temporal contiguous stores (register + immediate) defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>; defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index f86216025e1..59dcc4db7c2 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -574,6 +574,28 @@ multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList, (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } +class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList, + string asm, RegisterOperand gprty> +: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), + asm, "\t$Zt, $Pg, [$Rn, $Rm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rm; + bits<5> Rn; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-23} = sz; + let Inst{22-21} = nregs; + let Inst{20-16} = Rm; + let Inst{15-13} = 0b011; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + class sve_mem_cst_ss_base<bits<4> dtype, string asm, RegisterOperand listty, RegisterOperand gprty> : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), diff --git a/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s index 2f3bde8d1e4..07fdd64fe15 100644 --- a/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s @@ -30,6 +30,30 @@ st2b {z7.b, z8.b}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st2b { z0.b, z1.b }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2b { z0.b, z1.b }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2b { z0.b, z1.b }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2b { z0.b, z1.b }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st2b.s b/llvm/test/MC/AArch64/SVE/st2b.s index 8c501e9aad2..43266733d37 100644 --- a/llvm/test/MC/AArch64/SVE/st2b.s +++ b/llvm/test/MC/AArch64/SVE/st2b.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st2b { z0.b, z1.b }, p0, [x0, x0] +// CHECK-INST: st2b { z0.b, z1.b }, p0, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x20,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 e4 <unknown> + +st2b { z5.b, z6.b }, p3, [x17, x16] +// CHECK-INST: st2b { z5.b, z6.b }, p3, [x17, x16] +// CHECK-ENCODING: [0x25,0x6e,0x30,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 30 e4 <unknown> + st2b { z0.b, z1.b }, p0, [x0] // CHECK-INST: st2b { z0.b, z1.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x30,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s index 491e2f150e4..e5e09424484 100644 --- a/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s @@ -30,6 +30,35 @@ st2d {z7.d, z8.d}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st2d { z0.d, z1.d }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2d { z0.d, z1.d }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2d { z0.d, z1.d }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2d { z0.d, z1.d }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2d { z0.d, z1.d }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st2d.s b/llvm/test/MC/AArch64/SVE/st2d.s index c1cff0b3e1b..ac5f14c241d 100644 --- a/llvm/test/MC/AArch64/SVE/st2d.s +++ b/llvm/test/MC/AArch64/SVE/st2d.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3] +// CHECK-INST: st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0xa0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 a0 e5 <unknown> + +st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3] +// CHECK-INST: st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3] +// CHECK-ENCODING: [0x25,0x6e,0xb0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e b0 e5 <unknown> + st2d { z0.d, z1.d }, p0, [x0] // CHECK-INST: st2d { z0.d, z1.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe5] diff --git a/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s index f15a7956eb4..0854ada487e 100644 --- a/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s @@ -30,6 +30,35 @@ st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st2h { z0.h, z1.h }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2h { z0.h, z1.h }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2h { z0.h, z1.h }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st2h.s b/llvm/test/MC/AArch64/SVE/st2h.s index f7ffa6cfba0..7fc44efbb14 100644 --- a/llvm/test/MC/AArch64/SVE/st2h.s +++ b/llvm/test/MC/AArch64/SVE/st2h.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1] +// CHECK-INST: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xa0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 a0 e4 <unknown> + +st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1] +// CHECK-INST: st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1] +// CHECK-ENCODING: [0x25,0x6e,0xb0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e b0 e4 <unknown> + st2h { z0.h, z1.h }, p0, [x0] // CHECK-INST: st2h { z0.h, z1.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s index 2832751b204..61ca5ec964f 100644 --- a/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s @@ -30,6 +30,35 @@ st2w {z7.s, z8.s}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st2w { z0.s, z1.s }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2w { z0.s, z1.s }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2w { z0.s, z1.s }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2w { z0.s, z1.s }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2w { z0.s, z1.s }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st2w.s b/llvm/test/MC/AArch64/SVE/st2w.s index 4fc4df33963..723de51e54b 100644 --- a/llvm/test/MC/AArch64/SVE/st2w.s +++ b/llvm/test/MC/AArch64/SVE/st2w.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2] +// CHECK-INST: st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x20,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 e5 <unknown> + +st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2] +// CHECK-INST: st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2] +// CHECK-ENCODING: [0x25,0x6e,0x30,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 30 e5 <unknown> + st2w { z0.s, z1.s }, p0, [x0] // CHECK-INST: st2w { z0.s, z1.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x30,0xe5] diff --git a/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s index 36ffb6fc316..65201355482 100644 --- a/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s @@ -30,6 +30,30 @@ st3b {z7.b, z8.b, z9.b}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st3b { z0.b, z1.b, z2.b }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3b { z0.b, z1.b, z2.b }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3b { z0.b, z1.b, z2.b }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st3b.s b/llvm/test/MC/AArch64/SVE/st3b.s index f12817f6764..cda9e3d2a3e 100644 --- a/llvm/test/MC/AArch64/SVE/st3b.s +++ b/llvm/test/MC/AArch64/SVE/st3b.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st3b { z0.b, z1.b, z2.b }, p0, [x0, x0] +// CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 40 e4 <unknown> + +st3b { z5.b, z6.b, z7.b }, p3, [x17, x16] +// CHECK-INST: st3b { z5.b, z6.b, z7.b }, p3, [x17, x16] +// CHECK-ENCODING: [0x25,0x6e,0x50,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 50 e4 <unknown> + st3b { z0.b, z1.b, z2.b }, p0, [x0] // CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x50,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s index 8990e890525..c9e8591e446 100644 --- a/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s @@ -30,6 +30,35 @@ st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st3d { z0.d, z1.d, z2.d }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3d { z0.d, z1.d, z2.d }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st3d.s b/llvm/test/MC/AArch64/SVE/st3d.s index 319015ec633..1ef8f40e771 100644 --- a/llvm/test/MC/AArch64/SVE/st3d.s +++ b/llvm/test/MC/AArch64/SVE/st3d.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3] +// CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0xc0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 c0 e5 <unknown> + +st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3] +// CHECK-INST: st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3] +// CHECK-ENCODING: [0x25,0x6e,0xd0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e d0 e5 <unknown> + st3d { z0.d, z1.d, z2.d }, p0, [x0] // CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5] diff --git a/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s index 55d342bd9d0..f6874294cfc 100644 --- a/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s @@ -30,6 +30,35 @@ st3h {z7.h, z8.h, z9.h}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st3h { z0.h, z1.h, z2.h }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3h { z0.h, z1.h, z2.h }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3h { z0.h, z1.h, z2.h }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st3h.s b/llvm/test/MC/AArch64/SVE/st3h.s index 99b0e026cbc..d183d223668 100644 --- a/llvm/test/MC/AArch64/SVE/st3h.s +++ b/llvm/test/MC/AArch64/SVE/st3h.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1] +// CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 c0 e4 <unknown> + +st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1] +// CHECK-INST: st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1] +// CHECK-ENCODING: [0x25,0x6e,0xd0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e d0 e4 <unknown> + st3h { z0.h, z1.h, z2.h }, p0, [x0] // CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s index fb10614d013..9c2bb001049 100644 --- a/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s @@ -30,6 +30,35 @@ st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st3w { z0.s, z1.s, z2.s }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3w { z0.s, z1.s, z2.s }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st3w.s b/llvm/test/MC/AArch64/SVE/st3w.s index af2851154f4..69582c43016 100644 --- a/llvm/test/MC/AArch64/SVE/st3w.s +++ b/llvm/test/MC/AArch64/SVE/st3w.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2] +// CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 40 e5 <unknown> + +st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2] +// CHECK-INST: st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2] +// CHECK-ENCODING: [0x25,0x6e,0x50,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 50 e5 <unknown> + st3w { z0.s, z1.s, z2.s }, p0, [x0] // CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x50,0xe5] diff --git a/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s index cd1adec40b9..c316c81f03c 100644 --- a/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s @@ -30,6 +30,30 @@ st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st4b.s b/llvm/test/MC/AArch64/SVE/st4b.s index 6f4a6bd183b..c4a5cfcbb83 100644 --- a/llvm/test/MC/AArch64/SVE/st4b.s +++ b/llvm/test/MC/AArch64/SVE/st4b.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0] +// CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x60,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 e4 <unknown> + +st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16] +// CHECK-INST: st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16] +// CHECK-ENCODING: [0x25,0x6e,0x70,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 70 e4 <unknown> + st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] // CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x70,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s index f197e055444..87f4225a87c 100644 --- a/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s @@ -30,6 +30,36 @@ st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st4d.s b/llvm/test/MC/AArch64/SVE/st4d.s index 8bfdebb5383..1e93f7027bd 100644 --- a/llvm/test/MC/AArch64/SVE/st4d.s +++ b/llvm/test/MC/AArch64/SVE/st4d.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3] +// CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0xe0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 e0 e5 <unknown> + +st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3] +// CHECK-INST: st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3] +// CHECK-ENCODING: [0x25,0x6e,0xf0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e f0 e5 <unknown> + st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] // CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5] diff --git a/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s index d98e2ef7df2..e3cecfef021 100644 --- a/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s @@ -30,6 +30,35 @@ st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st4h.s b/llvm/test/MC/AArch64/SVE/st4h.s index 37e045a6554..526f357eeca 100644 --- a/llvm/test/MC/AArch64/SVE/st4h.s +++ b/llvm/test/MC/AArch64/SVE/st4h.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1] +// CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xe0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 e0 e4 <unknown> + +st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1] +// CHECK-INST: st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1] +// CHECK-ENCODING: [0x25,0x6e,0xf0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e f0 e4 <unknown> + st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] // CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4] diff --git a/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s index b823a18f2c5..46bb2d7d785 100644 --- a/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s @@ -30,6 +30,35 @@ st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL] // --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // error: restricted predicate has range [0, 7]. st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL] diff --git a/llvm/test/MC/AArch64/SVE/st4w.s b/llvm/test/MC/AArch64/SVE/st4w.s index 23a4f27c869..a52488dda38 100644 --- a/llvm/test/MC/AArch64/SVE/st4w.s +++ b/llvm/test/MC/AArch64/SVE/st4w.s @@ -7,6 +7,18 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2] +// CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x60,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 e5 <unknown> + +st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2] +// CHECK-INST: st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2] +// CHECK-ENCODING: [0x25,0x6e,0x70,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 6e 70 e5 <unknown> + st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] // CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] // CHECK-ENCODING: [0x00,0xe0,0x70,0xe5] |
