diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 50012569a74..631a1f7deca 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -206,7 +206,7 @@ def ixlenimm : Operand<XLenVT> { def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>; def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>; // A mask value that won't affect significant shift bits. -def immshiftxlen : ImmLeaf<XLenVT, [{ +def immbottomxlenset : ImmLeaf<XLenVT, [{ if (Subtarget->is64Bit()) return countTrailingOnes<uint64_t>(Imm) >= 6; return countTrailingOnes<uint64_t>(Imm) >= 5; @@ -660,15 +660,14 @@ def : PatGprUimmLog2XLen<sra, SRAI>; // typically introduced when the legalizer promotes the shift amount and // zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base // ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I). -multiclass VarShiftXLenPat<PatFrag ShiftOp, RVInst Inst> { - def : Pat<(ShiftOp GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; - def : Pat<(ShiftOp GPR:$rs1, (and GPR:$rs2, immshiftxlen)), - (Inst GPR:$rs1, GPR:$rs2)>; -} - -defm : VarShiftXLenPat<shl, SLL>; -defm : VarShiftXLenPat<srl, SRL>; -defm : VarShiftXLenPat<sra, SRA>; +class shiftop<SDPatternOperator operator> + : PatFrags<(ops node:$val, node:$count), + [(operator node:$val, node:$count), + (operator node:$val, (and node:$count, immbottomxlenset))]>; + +def : PatGprGpr<shiftop<shl>, SLL>; +def : PatGprGpr<shiftop<srl>, SRL>; +def : PatGprGpr<shiftop<sra>, SRA>; /// FrameIndex calculations |
