diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/intrinsics/trap.ll | 38 |
3 files changed, 51 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b67d4a85c32..4058af7328c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -193,6 +193,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Subtarget.is64Bit() ? Legal : Custom); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); + if (Subtarget.hasStdExtA()) { setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); setMinCmpXchgSizeInBits(32); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index db2ecc49d14..aaddecdc7d2 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1097,6 +1097,16 @@ let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">; +/// traps + +// We lower `trap` to `unimp`, as this causes a hard exception on nearly all +// systems. +def : Pat<(trap), (UNIMP)>; + +// We lower `debugtrap` to `ebreak`, as this will get the attention of the +// debugger if possible. +def : Pat<(debugtrap), (EBREAK)>; + //===----------------------------------------------------------------------===// // Standard extensions //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/intrinsics/trap.ll b/llvm/test/CodeGen/RISCV/intrinsics/trap.ll new file mode 100644 index 00000000000..e85073518ab --- /dev/null +++ b/llvm/test/CodeGen/RISCV/intrinsics/trap.ll @@ -0,0 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s + +; Verify that we lower @llvm.trap() and @llvm.debugtrap() correctly. + +declare void @llvm.trap() +declare void @llvm.debugtrap() + +define void @test_trap() nounwind { +; RV32I-LABEL: test_trap: +; RV32I: # %bb.0: +; RV32I-NEXT: unimp +; RV32I-NEXT: ret +; +; RV64I-LABEL: test_trap: +; RV64I: # %bb.0: +; RV64I-NEXT: unimp +; RV64I-NEXT: ret + tail call void @llvm.trap() + ret void +} + +define void @test_debugtrap() nounwind { +; RV32I-LABEL: test_debugtrap: +; RV32I: # %bb.0: +; RV32I-NEXT: ebreak +; RV32I-NEXT: ret +; +; RV64I-LABEL: test_debugtrap: +; RV64I: # %bb.0: +; RV64I-NEXT: ebreak +; RV64I-NEXT: ret + tail call void @llvm.debugtrap() + ret void +} |
