summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h5
-rw-r--r--llvm/lib/Analysis/TargetLibraryInfo.cpp13
-rw-r--r--llvm/lib/Bitcode/Reader/ValueList.cpp4
-rw-r--r--llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp3
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp4
-rw-r--r--llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp8
-rw-r--r--llvm/lib/Transforms/Utils/LowerSwitch.cpp5
-rw-r--r--llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp14
-rw-r--r--llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp21
9 files changed, 32 insertions, 45 deletions
diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h
index 86add501508..c083ecc6514 100644
--- a/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h
+++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFUnit.h
@@ -462,9 +462,8 @@ public:
DWARFDie getDIEForOffset(uint32_t Offset) {
extractDIEsIfNeeded(false);
assert(!DieArray.empty());
- auto it = std::lower_bound(
- DieArray.begin(), DieArray.end(), Offset,
- [](const DWARFDebugInfoEntry &LHS, uint32_t Offset) {
+ auto it = llvm::lower_bound(
+ DieArray, Offset, [](const DWARFDebugInfoEntry &LHS, uint32_t Offset) {
return LHS.getOffset() < Offset;
});
if (it != DieArray.end() && it->getOffset() == Offset)
diff --git a/llvm/lib/Analysis/TargetLibraryInfo.cpp b/llvm/lib/Analysis/TargetLibraryInfo.cpp
index d8b2af2f98b..10bb4ab17ca 100644
--- a/llvm/lib/Analysis/TargetLibraryInfo.cpp
+++ b/llvm/lib/Analysis/TargetLibraryInfo.cpp
@@ -1497,9 +1497,8 @@ bool TargetLibraryInfoImpl::isFunctionVectorizable(StringRef funcName) const {
if (funcName.empty())
return false;
- std::vector<VecDesc>::const_iterator I = std::lower_bound(
- VectorDescs.begin(), VectorDescs.end(), funcName,
- compareWithScalarFnName);
+ std::vector<VecDesc>::const_iterator I =
+ llvm::lower_bound(VectorDescs, funcName, compareWithScalarFnName);
return I != VectorDescs.end() && StringRef(I->ScalarFnName) == funcName;
}
@@ -1508,8 +1507,8 @@ StringRef TargetLibraryInfoImpl::getVectorizedFunction(StringRef F,
F = sanitizeFunctionName(F);
if (F.empty())
return F;
- std::vector<VecDesc>::const_iterator I = std::lower_bound(
- VectorDescs.begin(), VectorDescs.end(), F, compareWithScalarFnName);
+ std::vector<VecDesc>::const_iterator I =
+ llvm::lower_bound(VectorDescs, F, compareWithScalarFnName);
while (I != VectorDescs.end() && StringRef(I->ScalarFnName) == F) {
if (I->VectorizationFactor == VF)
return I->VectorFnName;
@@ -1524,8 +1523,8 @@ StringRef TargetLibraryInfoImpl::getScalarizedFunction(StringRef F,
if (F.empty())
return F;
- std::vector<VecDesc>::const_iterator I = std::lower_bound(
- ScalarDescs.begin(), ScalarDescs.end(), F, compareWithVectorFnName);
+ std::vector<VecDesc>::const_iterator I =
+ llvm::lower_bound(ScalarDescs, F, compareWithVectorFnName);
if (I == VectorDescs.end() || StringRef(I->VectorFnName) != F)
return StringRef();
VF = I->VectorizationFactor;
diff --git a/llvm/lib/Bitcode/Reader/ValueList.cpp b/llvm/lib/Bitcode/Reader/ValueList.cpp
index 4b482de640c..6cf1f4c1dd9 100644
--- a/llvm/lib/Bitcode/Reader/ValueList.cpp
+++ b/llvm/lib/Bitcode/Reader/ValueList.cpp
@@ -180,8 +180,8 @@ void BitcodeReaderValueList::resolveConstantForwardRefs() {
NewOp = RealVal;
} else {
// Otherwise, look up the placeholder in ResolveConstants.
- ResolveConstantsTy::iterator It = std::lower_bound(
- ResolveConstants.begin(), ResolveConstants.end(),
+ ResolveConstantsTy::iterator It = llvm::lower_bound(
+ ResolveConstants,
std::pair<Constant *, unsigned>(cast<Constant>(*I), 0));
assert(It != ResolveConstants.end() && It->first == *I);
NewOp = operator[](It->second);
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index dc7ba937acb..290d592339f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -535,8 +535,7 @@ bool IRTranslator::translateExtractValue(const User &U,
uint64_t Offset = getOffsetFromIndices(U, *DL);
ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
- unsigned Idx = std::lower_bound(Offsets.begin(), Offsets.end(), Offset) -
- Offsets.begin();
+ unsigned Idx = llvm::lower_bound(Offsets, Offset) - Offsets.begin();
auto &DstRegs = allocateVRegs(U);
for (unsigned i = 0; i < DstRegs.size(); ++i)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 761d09edef4..defc30b2c8c 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2262,8 +2262,8 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
LLVM_DEBUG(dbgs() << RMS.size() << " regmasks in block:");
// Constrain to VirtReg's live range.
- unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
- Uses.front().getRegSlot()) - RMS.begin();
+ unsigned ri =
+ llvm::lower_bound(RMS, Uses.front().getRegSlot()) - RMS.begin();
unsigned re = RMS.size();
for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
// Look for Uses[i] <= RMS <= Uses[i+1].
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
index 6bac12f765d..7c80b3bb3e9 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp
@@ -57,8 +57,8 @@ void DWARFDebugLoc::LocationList::dump(raw_ostream &OS, bool IsLittleEndian,
DWARFDebugLoc::LocationList const *
DWARFDebugLoc::getLocationListAtOffset(uint64_t Offset) const {
- auto It = std::lower_bound(
- Locations.begin(), Locations.end(), Offset,
+ auto It = llvm::lower_bound(
+ Locations, Offset,
[](const LocationList &L, uint64_t Offset) { return L.Offset < Offset; });
if (It != Locations.end() && It->Offset == Offset)
return &(*It);
@@ -213,8 +213,8 @@ void DWARFDebugLoclists::parse(DataExtractor data, unsigned Version) {
DWARFDebugLoclists::LocationList const *
DWARFDebugLoclists::getLocationListAtOffset(uint64_t Offset) const {
- auto It = std::lower_bound(
- Locations.begin(), Locations.end(), Offset,
+ auto It = llvm::lower_bound(
+ Locations, Offset,
[](const LocationList &L, uint64_t Offset) { return L.Offset < Offset; });
if (It != Locations.end() && It->Offset == Offset)
return &(*It);
diff --git a/llvm/lib/Transforms/Utils/LowerSwitch.cpp b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
index 3c973e7c142..680b5d31a42 100644
--- a/llvm/lib/Transforms/Utils/LowerSwitch.cpp
+++ b/llvm/lib/Transforms/Utils/LowerSwitch.cpp
@@ -62,9 +62,8 @@ static bool IsInRanges(const IntRange &R,
// Find the first range whose High field is >= R.High,
// then check if the Low field is <= R.Low. If so, we
// have a Range that covers R.
- auto I = std::lower_bound(
- Ranges.begin(), Ranges.end(), R,
- [](const IntRange &A, const IntRange &B) { return A.High < B.High; });
+ auto I = llvm::lower_bound(
+ Ranges, R, [](IntRange A, IntRange B) { return A.High < B.High; });
return I != Ranges.end() && I->Low <= R.Low;
}
diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
index 5748b06a76b..b0fb427c40e 100644
--- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -487,11 +487,10 @@ static bool promoteSingleBlockAlloca(AllocaInst *AI, const AllocaInfo &Info,
unsigned LoadIdx = LBI.getInstructionIndex(LI);
// Find the nearest store that has a lower index than this load.
- StoresByIndexTy::iterator I =
- std::lower_bound(StoresByIndex.begin(), StoresByIndex.end(),
- std::make_pair(LoadIdx,
- static_cast<StoreInst *>(nullptr)),
- less_first());
+ StoresByIndexTy::iterator I = llvm::lower_bound(
+ StoresByIndex,
+ std::make_pair(LoadIdx, static_cast<StoreInst *>(nullptr)),
+ less_first());
if (I == StoresByIndex.begin()) {
if (StoresByIndex.empty())
// If there are no stores, the load takes the undef value.
@@ -758,9 +757,8 @@ void PromoteMem2Reg::run() {
// them from the Preds list.
for (unsigned i = 0, e = SomePHI->getNumIncomingValues(); i != e; ++i) {
// Do a log(n) search of the Preds list for the entry we want.
- SmallVectorImpl<BasicBlock *>::iterator EntIt = std::lower_bound(
- Preds.begin(), Preds.end(), SomePHI->getIncomingBlock(i),
- CompareBBNumbers);
+ SmallVectorImpl<BasicBlock *>::iterator EntIt = llvm::lower_bound(
+ Preds, SomePHI->getIncomingBlock(i), CompareBBNumbers);
assert(EntIt != Preds.end() && *EntIt == SomePHI->getIncomingBlock(i) &&
"PHI node has entry for a block which is not a predecessor!");
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
index 84ef7ac0f27..4a696e2e7d3 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
@@ -21,7 +21,6 @@
static constexpr const char kIntegerPrefix[] = "i_0x";
static constexpr const char kDoublePrefix[] = "f_";
static constexpr const char kInvalidOperand[] = "INVALID";
-static constexpr llvm::StringLiteral kNoRegister("%noreg");
namespace llvm {
@@ -48,9 +47,7 @@ struct YamlContext {
llvm::StringMap<unsigned>
generateRegNameToRegNoMapping(const llvm::MCRegisterInfo &RegInfo) {
llvm::StringMap<unsigned> Map(RegInfo.getNumRegs());
- // Special-case RegNo 0, which would otherwise be spelled as ''.
- Map[kNoRegister] = 0;
- for (unsigned I = 1, E = RegInfo.getNumRegs(); I < E; ++I)
+ for (unsigned I = 0, E = RegInfo.getNumRegs(); I < E; ++I)
Map[RegInfo.getName(I)] = I;
assert(Map.size() == RegInfo.getNumRegs() && "Size prediction failed");
return Map;
@@ -86,21 +83,18 @@ struct YamlContext {
llvm::raw_string_ostream &getErrorStream() { return ErrorStream; }
llvm::StringRef getRegName(unsigned RegNo) {
- // Special case: RegNo 0 is NoRegister. We have to deal with it explicitly.
- if (RegNo == 0)
- return kNoRegister;
const llvm::StringRef RegName = State->getRegInfo().getName(RegNo);
if (RegName.empty())
ErrorStream << "No register with enum value '" << RegNo << "'\n";
return RegName;
}
- llvm::Optional<unsigned> getRegNo(llvm::StringRef RegName) {
+ unsigned getRegNo(llvm::StringRef RegName) {
auto Iter = RegNameToRegNo.find(RegName);
if (Iter != RegNameToRegNo.end())
return Iter->second;
ErrorStream << "No register with name '" << RegName << "'\n";
- return llvm::None;
+ return 0;
}
private:
@@ -148,8 +142,8 @@ private:
return llvm::MCOperand::createImm(IntValue);
if (tryDeserializeFPOperand(String, DoubleValue))
return llvm::MCOperand::createFPImm(DoubleValue);
- if (auto RegNo = getRegNo(String))
- return llvm::MCOperand::createReg(*RegNo);
+ if (unsigned RegNo = getRegNo(String))
+ return llvm::MCOperand::createReg(RegNo);
if (String != kInvalidOperand)
ErrorStream << "Unknown Operand: '" << String << "'\n";
return {};
@@ -264,9 +258,8 @@ template <> struct ScalarTraits<exegesis::RegisterValue> {
String.split(Pieces, "=0x", /* MaxSplit */ -1,
/* KeepEmpty */ false);
YamlContext &Context = getTypedContext(Ctx);
- llvm::Optional<unsigned> RegNo;
- if (Pieces.size() == 2 && (RegNo = Context.getRegNo(Pieces[0]))) {
- RV.Register = *RegNo;
+ if (Pieces.size() == 2) {
+ RV.Register = Context.getRegNo(Pieces[0]);
const unsigned BitsNeeded = llvm::APInt::getBitsNeeded(Pieces[1], kRadix);
RV.Value = llvm::APInt(BitsNeeded, Pieces[1], kRadix);
} else {
OpenPOWER on IntegriCloud