6 files changed, 20 insertions, 9 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index c06e4b57044..e05e9159427 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -478,11 +478,11 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
   MaxSGPR += ExtraSGPRs;
 
   // Update necessary Reserved* fields and max VGPRs used if
-  // "amdgpu-debugger-reserved-trap-regs" was specified.
+  // "amdgpu-debugger-reserve-trap-regs" attribute was specified.
   if (STM.debuggerReserveTrapVGPRs()) {
     ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
-    ProgInfo.ReservedVGPRCount = STM.debuggerReserveTrapVGPRCount();
-    MaxVGPR += STM.debuggerReserveTrapVGPRCount();
+    ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
+    MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
   }
 
   // We found the maximum register index. They start at 0, so add one to get the
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index acadcc0ebf0..87f953fce27 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -69,7 +69,10 @@ private:
     uint32_t LDSSize;
     bool FlatUsed;
 
+    // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first
+    // fixed VGPR number reserved.
     uint16_t ReservedVGPRFirst;
+    // The number of consecutive VGPRs reserved.
     uint16_t ReservedVGPRCount;
 
     // Bonus information for debugging.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 12e6fee7d26..d794039d6fe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -314,10 +314,6 @@ public:
     return DebuggerReserveTrapVGPRs;
   }
 
-  unsigned debuggerReserveTrapVGPRCount() const {
-    return debuggerReserveTrapVGPRs() ? 4 : 0;
-  }
-
   bool dumpCode() const {
     return DumpCode;
   }
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index d42c7c1e2ba..d10a9c1a846 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -49,6 +49,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
     PSInputAddr(0),
     ReturnsVoid(true),
     MaximumWorkGroupSize(0),
+    DebuggerReserveTrapVGPRCount(0),
     LDSWaveSpillSize(0),
     PSInputEna(0),
     NumUserSGPRs(0),
@@ -132,6 +133,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
     MaximumWorkGroupSize = AMDGPU::getMaximumWorkGroupSize(*F);
   else
     MaximumWorkGroupSize = ST.getWavefrontSize();
+
+  if (ST.debuggerReserveTrapVGPRs())
+    DebuggerReserveTrapVGPRCount = 4;
 }
 
 unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index aa59602341b..04437f1d894 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -62,6 +62,9 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
 
   unsigned MaximumWorkGroupSize;
 
+  // Number of reserved VGPRs for trap handler usage.
+  unsigned DebuggerReserveTrapVGPRCount;
+
 public:
   // FIXME: Make private
   unsigned LDSWaveSpillSize;
@@ -326,6 +329,10 @@ public:
     ReturnsVoid = Value;
   }
 
+  unsigned getDebuggerReserveTrapVGPRCount() const {
+    return DebuggerReserveTrapVGPRCount;
+  }
+
   unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
 };
 
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 1f09500ebf1..4bc89ea2773 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -197,8 +197,9 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // attribute was specified.
   const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
   if (ST.debuggerReserveTrapVGPRs()) {
-    for (unsigned i = MaxWorkGroupVGPRCount - ST.debuggerReserveTrapVGPRCount();
-           i < MaxWorkGroupVGPRCount; ++i) {
+    unsigned ReservedVGPRFirst =
+      MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
+    for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
       unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
       reserveRegisterTuples(Reserved, Reg);
     }