diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/bool-math.ll | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/bool-math.ll b/llvm/test/CodeGen/X86/bool-math.ll new file mode 100644 index 00000000000..9095dd44298 --- /dev/null +++ b/llvm/test/CodeGen/X86/bool-math.ll @@ -0,0 +1,117 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s + +define i32 @sub_zext_cmp_mask_wider_result(i8 %x) { +; CHECK-LABEL: sub_zext_cmp_mask_wider_result: +; CHECK: # %bb.0: +; CHECK-NEXT: andb $1, %dil +; CHECK-NEXT: cmpb $1, %dil +; CHECK-NEXT: movl $27, %eax +; CHECK-NEXT: sbbl $0, %eax +; CHECK-NEXT: retq + %a = and i8 %x, 1 + %c = icmp eq i8 %a, 0 + %z = zext i1 %c to i32 + %r = sub i32 27, %z + ret i32 %r +} + +define i8 @sub_zext_cmp_mask_narrower_result(i32 %x) { +; CHECK-LABEL: sub_zext_cmp_mask_narrower_result: +; CHECK: # %bb.0: +; CHECK-NEXT: andl $1, %edi +; CHECK-NEXT: cmpl $1, %edi +; CHECK-NEXT: movb $47, %al +; CHECK-NEXT: sbbb $0, %al +; CHECK-NEXT: retq + %a = and i32 %x, 1 + %c = icmp eq i32 %a, 0 + %z = zext i1 %c to i8 + %r = sub i8 47, %z + ret i8 %r +} + +define i32 @add_zext_cmp_mask_wider_result(i8 %x) { +; CHECK-LABEL: add_zext_cmp_mask_wider_result: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: sete %al +; CHECK-NEXT: orl $26, %eax +; CHECK-NEXT: retq + %a = and i8 %x, 1 + %c = icmp eq i8 %a, 0 + %z = zext i1 %c to i32 + %r = add i32 %z, 26 + ret i32 %r +} + +define i8 @add_zext_cmp_mask_narrower_result(i32 %x) { +; CHECK-LABEL: add_zext_cmp_mask_narrower_result: +; CHECK: # %bb.0: +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: sete %al +; CHECK-NEXT: orb $42, %al +; CHECK-NEXT: retq + %a = and i32 %x, 1 + %c = icmp eq i32 %a, 0 + %z = zext i1 %c to i8 + %r = add i8 %z, 42 + ret i8 %r +} + +define i64 @low_bit_select_constants_bigger_false_wider_result(i32 %x) { +; CHECK-LABEL: low_bit_select_constants_bigger_false_wider_result: +; CHECK: # %bb.0: +; CHECK-NEXT: andl $1, %edi +; CHECK-NEXT: cmpl $1, %edi +; CHECK-NEXT: movl $27, %eax +; CHECK-NEXT: sbbq $0, %rax +; CHECK-NEXT: retq + %a = and i32 %x, 1 + %c = icmp eq i32 %a, 0 + %r = select i1 %c, i64 26, i64 27 + ret i64 %r +} + +define i16 @low_bit_select_constants_bigger_false_narrower_result(i32 %x) { +; CHECK-LABEL: low_bit_select_constants_bigger_false_narrower_result: +; CHECK: # %bb.0: +; CHECK-NEXT: andl $1, %edi +; CHECK-NEXT: cmpl $1, %edi +; CHECK-NEXT: movw $37, %ax +; CHECK-NEXT: sbbw $0, %ax +; CHECK-NEXT: retq + %a = and i32 %x, 1 + %c = icmp eq i32 %a, 0 + %r = select i1 %c, i16 36, i16 37 + ret i16 %r +} + +define i32 @low_bit_select_constants_bigger_true_wider_result(i8 %x) { +; CHECK-LABEL: low_bit_select_constants_bigger_true_wider_result: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: sete %al +; CHECK-NEXT: orl $226, %eax +; CHECK-NEXT: retq + %a = and i8 %x, 1 + %c = icmp eq i8 %a, 0 + %r = select i1 %c, i32 227, i32 226 + ret i32 %r +} + +define i8 @low_bit_select_constants_bigger_true_narrower_result(i16 %x) { +; CHECK-LABEL: low_bit_select_constants_bigger_true_narrower_result: +; CHECK: # %bb.0: +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: sete %al +; CHECK-NEXT: orb $40, %al +; CHECK-NEXT: retq + %a = and i16 %x, 1 + %c = icmp eq i16 %a, 0 + %r = select i1 %c, i8 41, i8 40 + ret i8 %r +} + |
