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-rw-r--r--llvm/lib/Target/Mips/Mips32r6InstrInfo.td5
-rw-r--r--llvm/lib/Target/Mips/Mips64r6InstrInfo.td3
-rw-r--r--llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll60
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/call.ll22
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll2
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/ret.ll8
-rw-r--r--llvm/test/CodeGen/Mips/mips64-f128.ll10
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt2
-rw-r--r--llvm/test/MC/Mips/mips32r6/valid.s2
-rw-r--r--llvm/test/MC/Mips/mips64r6/valid.s2
13 files changed, 73 insertions, 49 deletions
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 3e2c8293c26..337975c276f 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -815,8 +815,11 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
}
-def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
+def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
+def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
+
+def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
//===----------------------------------------------------------------------===//
//
// Patterns and Pseudo Instructions
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index d11f2a2890a..f9e5154bc7d 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -131,6 +131,9 @@ def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
+def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
+
+def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6;
//===----------------------------------------------------------------------===//
//
// Patterns and Pseudo Instructions
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
index b489a23f69e..a7e92195ee9 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
@@ -4,9 +4,9 @@
; Function Attrs: nounwind
define void @l() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call1 = tail call i32 @j()
%cmp = icmp eq i32 %call, %call1
; CHECK: bnec
@@ -15,12 +15,12 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext -2)
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
@@ -33,9 +33,9 @@ declare void @f(i32 signext)
; Function Attrs: define void @l2() {
define void @l2() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call1 = tail call i32 @i()
%cmp = icmp eq i32 %call, %call1
; CHECK beqc
@@ -44,12 +44,12 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext -1)
br label %if.end
if.end: ; preds = %entry, %if.then
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
@@ -58,7 +58,7 @@ declare i32 @i()
; Function Attrs: nounwind
define void @l3() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
%cmp = icmp slt i32 %call, 0
; CHECK : bgez
@@ -67,12 +67,12 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext 0)
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
@@ -91,16 +91,16 @@ if.then: ; preds = %entry:
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
; Function Attrs: nounwind
define void @l5() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%cmp = icmp sgt i32 %call, 0
; CHECK: blezc
br i1 %cmp, label %if.then, label %if.end
@@ -108,21 +108,21 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext 2)
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
; Function Attrs: nounwind
define void @l6() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%cmp = icmp sgt i32 %call, -1
; CHECK: bltzc
br i1 %cmp, label %if.then, label %if.end
@@ -130,19 +130,19 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext 3)
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
; Function Attrs: nounwind
define void @l7() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
%cmp = icmp eq i32 %call, 0
; CHECK: bnezc
@@ -151,19 +151,19 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext 4)
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
; Function Attrs: nounwind
define void @l8() {
entry:
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = tail call i32 @k()
%cmp = icmp eq i32 %call, 0
; CHECK: beqzc
@@ -172,12 +172,12 @@ entry:
if.then: ; preds = %entry:
; STATIC: nop
; STATIC: jal
-; PIC: jialc $25, 0
+; PIC: jalrc $25
tail call void @f(i32 signext 5)
br label %if.end
if.end: ; preds = %entry, %if.then
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret void
}
@@ -187,20 +187,20 @@ entry:
store i8* ()* %i, i8* ()** %i.addr, align 4
; STATIC32: jal
; STATIC32: nop
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%call = call i32 @k()
-; PIC: jialc $25, 0
+; PIC: jalrc $25
%cmp = icmp ne i32 %call, 0
; CHECK: beqzc
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%0 = load i8* ()*, i8* ()** %i.addr, align 4
-; CHECK: jialc $25, 0
+; CHECK: jalrc $25
%call1 = call i8* %0()
br label %if.end
if.end: ; preds = %if.then, %entry
-; CHECK: jic $ra, 0
+; CHECK: jrc $ra
ret i32 -1
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
index da3ffaf64b1..063b7465aed 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
@@ -26,9 +26,10 @@ define i32 @call_void_void() {
; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp)
; NOT-R6C: jalr $[[TGT]]
-; R6C: jialc $[[TGT]], 0
+; R6C: jalrc $[[TGT]]
call void @extern_void_void()
+; R6C: jrc $ra
ret i32 0
}
@@ -40,10 +41,11 @@ define i32 @call_i32_void() {
; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp)
; NOT-R6C: jalr $[[TGT]]
-; R6C: jialc $[[TGT]], 0
+; R6C: jalrc $[[TGT]]
%1 = call i32 @extern_i32_void()
%2 = add i32 %1, 1
+; R6C: jrc $ra
ret i32 %2
}
@@ -58,11 +60,12 @@ define float @call_float_void() {
; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp)
; NOT-R6C: jalr $[[TGT]]
-; R6C: jialc $[[TGT]], 0
+; R6C: jalrc $[[TGT]]
%1 = call float @extern_float_void()
%2 = fadd float %1, 1.0
+; R6C: jrc $ra
ret float %2
}
@@ -110,10 +113,10 @@ define i32 @indirect_call_void_void(void ()* %addr) {
; ALL: move $25, $4
; NOT-R6C: jalr $25
-; R6C: jialc $25, 0
-
+; R6C: jalrc $25
call void %addr()
+; R6C: jrc $ra
ret i32 0
}
@@ -122,11 +125,12 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) {
; ALL: move $25, $4
; NOT-R6C: jalr $25
-; R6C: jialc $25, 0
+; R6C: jalrc $25
%1 = call i32 %addr()
%2 = add i32 %1, 1
+; R6C: jrc $ra
ret i32 %2
}
@@ -135,11 +139,12 @@ define float @indirect_call_float_void(float ()* %addr) {
; ALL: move $25, $4
; NOT-R6C: jalr $25
-; R6C: jialc $25, 0
+; R6C: jalrc $25
%1 = call float %addr()
%2 = fadd float %1, 1.0
+; R6C: jrc $ra
ret float %2
}
@@ -197,10 +202,11 @@ define i32 @jal_only_allows_symbols() {
; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234
; ALL-NOT: {{jal }}
; NOT-R6C: jalr $[[TGT]]
-; R6C: jialc $[[TGT]], 0
+; R6C: jalrc $[[TGT]]
; ALL-NOT: {{jal }}
call void () inttoptr (i32 1234 to void ()*)()
+; R6C: jrc $ra
ret i32 0
}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index 4fdce5a0490..26c02edee51 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -15,7 +15,7 @@
define i32 @br(i8 *%addr) {
; ALL-LABEL: br:
; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
-; R6C: jic $4, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC
; ALL: $BB0_1: # %L1
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
index de104f97551..e2bfd9f6d04 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -31,7 +31,7 @@ define void @ret_void() {
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
ret void
}
@@ -181,7 +181,7 @@ define float @ret_float_0x3() {
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
; float constants are written as double constants
ret float 0x36b8000000000000
@@ -200,7 +200,7 @@ define double @ret_double_0x0() {
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
ret double 0x0000000000000000
}
@@ -214,7 +214,7 @@ define double @ret_double_0x3() {
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
-; R6C-DAG: jic $ra, 0 # <MCInst #{{[0-9]+}} JIC
+; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC
ret double 0x0000000000000003
}
diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll
index 66a2f95cde2..81fd3b889f2 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128.ll
@@ -548,7 +548,7 @@ entry:
; ALL: lw $4, 0($[[R0]])
; ALL: ld $25, %call16(__extendsftf2)
; PRER6: jalr $25
-; R6: jialc $25, 0
+; R6: jalrc $25
define fp128 @load_LD_float() {
entry:
@@ -562,7 +562,7 @@ entry:
; ALL: ld $4, 0($[[R0]])
; ALL: ld $25, %call16(__extenddftf2)
; PRER6: jalr $25
-; R6: jialc $25, 0
+; R6: jalrc $25
define fp128 @load_LD_double() {
entry:
@@ -592,7 +592,7 @@ entry:
; ALL: ld $5, 8($[[R0]])
; ALL: ld $25, %call16(__trunctfsf2)
; PRER6: jalr $25
-; R6: jialc $25, 0
+; R6: jalrc $25
; ALL: ld $[[R1:[0-9]+]], %got_disp(gf1)
; ALL: sw $2, 0($[[R1]])
@@ -610,7 +610,7 @@ entry:
; ALL: ld $5, 8($[[R0]])
; ALL: ld $25, %call16(__trunctfdf2)
; PRER6: jalr $25
-; R6: jialc $25, 0
+; R6: jalrc $25
; ALL: ld $[[R1:[0-9]+]], %got_disp(gd1)
; ALL: sd $2, 0($[[R1]])
@@ -653,7 +653,7 @@ entry:
; ALL: move $[[R3:[0-9]+]], $8
; ALL: ld $25, %call16(__gttf2)($gp)
; PRER6: jalr $25
-; R6: jialc $25, 0
+; R6: jalrc $25
; C_CC_FMT: slti $[[CC:[0-9]+]], $2, 1
; C_CC_FMT: movz $[[R1]], $[[R3]], $[[CC]]
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 4164988b2b8..0714578f475 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -117,8 +117,10 @@
0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
+0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)
0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 6af02fc61b8..0b5f38f1e38 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -18,8 +18,10 @@
0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
+0xd8 0x1b 0x00 0x00 # CHECK: jrc $27
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0xf8 0x19 0x00 0x00 # CHECK: jalrc $25
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index 08f5e04ab4f..ebc18e435ef 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -104,8 +104,10 @@
0x20 0x60 0x6e 0x41 # CHECK: ei $14
0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5
+0x00 0x00 0x19 0xf8 # CHECK: jalrc $25
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 7fa27a7c542..83edbb6eb3b 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -29,8 +29,10 @@
0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
+0xd8 0x1b 0x00 0x00 # CHECK: jrc $27
0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
+0xf8 0x19 0x00 0x00 # CHECK: jalrc $25
0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5
0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index 8e759a0ee6b..c88999339fe 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -163,8 +163,10 @@ a:
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
jr $ra # CHECK: jr $ra # encoding: [0x03,0xe0,0x00,0x09]
jr $25 # CHECK: jr $25 # encoding: [0x03,0x20,0x00,0x09]
+ jrc $27 # CHECK: jrc $27 # encoding: [0xd8,0x1b,0x00,0x00]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+ jalrc $25 # CHECK: jalrc $25 # encoding: [0xf8,0x19,0x00,0x00]
jialc $15, 16161 # CHECK: jialc $15, 16161 # encoding: [0xf8,0x0f,0x3f,0x21]
jic $12, -3920 # CHECK: jic $12, -3920 # encoding: [0xd8,0x0c,0xf0,0xb0]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s
index f70354fba6b..53107ceb321 100644
--- a/llvm/test/MC/Mips/mips64r6/valid.s
+++ b/llvm/test/MC/Mips/mips64r6/valid.s
@@ -142,8 +142,10 @@ a:
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
jr $ra # CHECK: jr $ra # encoding: [0x03,0xe0,0x00,0x09]
jr $25 # CHECK: jr $25 # encoding: [0x03,0x20,0x00,0x09]
+ jrc $27 # CHECK: jrc $27 # encoding: [0xd8,0x1b,0x00,0x00]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
+ jalrc $25 # CHECK: jalrc $25 # encoding: [0xf8,0x19,0x00,0x00]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43]
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