diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 8 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 07e593afb7c..41d1d5d9251 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1734,8 +1734,8 @@ namespace ISD { static const uint64_t NestOffs = 5; static const uint64_t ByValAlign = 0xFULL << 6; //< Struct alignment static const uint64_t ByValAlignOffs = 6; - static const uint64_t Divided = 1ULL << 10; - static const uint64_t DividedOffs = 10; + static const uint64_t Split = 1ULL << 10; + static const uint64_t SplitOffs = 10; static const uint64_t OrigAlign = 0x1FULL<<27; static const uint64_t OrigAlignOffs = 27; static const uint64_t ByValSize = 0xffffffffULL << 32; //< Struct size @@ -1773,8 +1773,8 @@ namespace ISD { (uint64_t(Log2_32(A) + 1) << ByValAlignOffs); } - bool isDivided() const { return Flags & Divided; } - void setDivided() { Flags |= One << DividedOffs; } + bool isSplit() const { return Flags & Split; } + void setSplit() { Flags |= One << SplitOffs; } unsigned getOrigAlign() const { return (One << ((Flags & OrigAlign) >> OrigAlignOffs)) / 2; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index f37280895c3..c9b334fc22c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4164,7 +4164,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { RetVals.push_back(RegisterVT); ISD::ArgFlagsTy MyFlags = Flags; if (NumRegs > 1 && i == 0) - MyFlags.setDivided(); + MyFlags.setSplit(); // if it isn't first piece, alignment must be 1 else if (i > 0) MyFlags.setOrigAlign(1); @@ -4289,7 +4289,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // if it isn't first piece, alignment must be 1 ISD::ArgFlagsTy MyFlags = Flags; if (NumParts > 1 && i == 0) - MyFlags.setDivided(); + MyFlags.setSplit(); else if (i != 0) MyFlags.setOrigAlign(1); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index b1643904652..83bea7e11c2 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1423,7 +1423,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); // See if next argument requires stack alignment in ELF - bool Align = Flags.isDivided(); + bool Align = Flags.isSplit(); unsigned CurArgOffset = ArgOffset; @@ -1855,7 +1855,7 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, ISD::ArgFlagsTy Flags = cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); // See if next argument requires stack alignment in ELF - bool Align = Flags.isDivided(); + bool Align = Flags.isSplit(); // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. |
