diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/i64-mem-copy.ll | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f36e4a5e369..6e6285e44fc 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23315,7 +23315,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, SDValue OldExtract = St->getOperand(1); SDValue ExtOp0 = OldExtract.getOperand(0); unsigned VecSize = ExtOp0.getValueSizeInBits(); - MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64); + EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64); SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0); SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, BitCast, OldExtract.getOperand(1)); diff --git a/llvm/test/CodeGen/X86/i64-mem-copy.ll b/llvm/test/CodeGen/X86/i64-mem-copy.ll index 95715ea08eb..69ec3fd806b 100644 --- a/llvm/test/CodeGen/X86/i64-mem-copy.ll +++ b/llvm/test/CodeGen/X86/i64-mem-copy.ll @@ -63,3 +63,14 @@ define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, i64* %i) { ret void } +; PR23476 +; Handle extraction from a non-simple / pre-legalization type. + +define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) { +; X32-LABEL: PR23476: +; X32: movsd {{.*#+}} xmm0 = mem[0],zero +; X32-NEXT: movsd %xmm0, (%eax) + %ext = extractelement <5 x i64> %in, i32 %index + store i64 %ext, i64* %out, align 8 + ret void +} |
