diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/call-ret-i1.ll | 23 |
2 files changed, 25 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index bece022eabf..bd5050aae30 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -677,13 +677,14 @@ SDValue HexagonTargetLowering::LowerCallResult( // as an implicit def to the call (EmitMachineNode). RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); Glue = TPR.getValue(1); + Chain = TPR.getValue(0); } else { RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), RVLocs[i].getValVT(), Glue); Glue = RetVal.getValue(2); + Chain = RetVal.getValue(1); } InVals.push_back(RetVal.getValue(0)); - Chain = RetVal.getValue(1); } return Chain; diff --git a/llvm/test/CodeGen/Hexagon/call-ret-i1.ll b/llvm/test/CodeGen/Hexagon/call-ret-i1.ll new file mode 100644 index 00000000000..3838e8a6e88 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/call-ret-i1.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; Test that the compiler does not assert because the DAG is not correct. +; CHECK: call foo + +%returntype = type { i1, i32 } + +define i32 @test(i32* %a0, i32* %a1, i32* %a2) #0 { +b3: + br i1 undef, label %b6, label %b4 + +b4: ; preds = %b3 + %v5 = call %returntype @foo(i32* nonnull undef, i32* %a2, i32* %a0) #0 + ret i32 1 + +b6: ; preds = %b3 + unreachable +} + +declare %returntype @foo(i32*, i32*, i32*) #0 + +attributes #0 = { nounwind } |
