diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/gicv3-regs.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 2162775c369..2630d697bee 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -451,7 +451,7 @@ def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; -def : ROSysReg<"ICH_ELSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; +def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; // v8.1a "Limited Ordering Regions" extension-specific system register // Op0 Op1 CRn CRm Op2 diff --git a/llvm/test/MC/AArch64/gicv3-regs.s b/llvm/test/MC/AArch64/gicv3-regs.s index 0f5742ee543..ed3599fc956 100644 --- a/llvm/test/MC/AArch64/gicv3-regs.s +++ b/llvm/test/MC/AArch64/gicv3-regs.s @@ -7,7 +7,7 @@ mrs x29, icc_rpr_el1 mrs x4, ich_vtr_el2 mrs x24, ich_eisr_el2 - mrs x9, ich_elsr_el2 + mrs x9, ich_elrsr_el2 mrs x24, icc_bpr1_el1 mrs x14, icc_bpr0_el1 mrs x19, icc_pmr_el1 @@ -63,7 +63,7 @@ // CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} // encoding: [0x7d,0xcb,0x38,0xd5] // CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} // encoding: [0x24,0xcb,0x3c,0xd5] // CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} // encoding: [0x78,0xcb,0x3c,0xd5] -// CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5] +// CHECK: mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5] // CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} // encoding: [0x78,0xcc,0x38,0xd5] // CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} // encoding: [0x6e,0xc8,0x38,0xd5] // CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} // encoding: [0x13,0x46,0x38,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt index 851e83dab7f..aec30c662f7 100644 --- a/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt +++ b/llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt @@ -16,7 +16,7 @@ 0x78 0xcb 0x3c 0xd5 # CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 0xa9 0xcb 0x3c 0xd5 -# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} +# CHECK: mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}} 0x78 0xcc 0x38 0xd5 # CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 0x6e 0xc8 0x38 0xd5 |
