diff options
| -rw-r--r-- | llvm/lib/CodeGen/MachineBasicBlock.cpp | 27 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir | 33 |
2 files changed, 45 insertions, 15 deletions
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 0b9ee462d1a..03771bc5dae 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1380,24 +1380,21 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, // Try searching forwards from Before, looking for reads or defs. const_iterator I(Before); - // If this is the last insn in the block, don't search forwards. - if (I != end()) { - for (++I; I != end() && N > 0; ++I) { - if (I->isDebugInstr()) - continue; + for (; I != end() && N > 0; ++I) { + if (I->isDebugInstr()) + continue; - --N; + --N; - MachineOperandIteratorBase::PhysRegInfo Info = - ConstMIOperands(*I).analyzePhysReg(Reg, TRI); + MachineOperandIteratorBase::PhysRegInfo Info = + ConstMIOperands(*I).analyzePhysReg(Reg, TRI); - // Register is live when we read it here. - if (Info.Read) - return LQR_Live; - // Register is dead if we can fully overwrite or clobber it here. - if (Info.FullyDefined || Info.Clobbered) - return LQR_Dead; - } + // Register is live when we read it here. + if (Info.Read) + return LQR_Live; + // Register is dead if we can fully overwrite or clobber it here. + if (Info.FullyDefined || Info.Clobbered) + return LQR_Dead; } // If we reached the end, it is safe to clobber Reg at the end of a block of diff --git a/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir b/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir new file mode 100644 index 00000000000..7a4db88479b --- /dev/null +++ b/llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir @@ -0,0 +1,33 @@ +# RUN: llc -mtriple=thumbv6m--eabi -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s + +# Make sure bb.0 isn't transformed: it would incorrectly clobber CPSR. +# +# Make sure bb.1 is transformed, so the test doesn't accidentally break. + +# CHECK-LABEL: bb.0: +# CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4) +# CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4) + +# CHECK-LABEL: bb.1: +# CHECK: $r4 = tLDMIA_UPD $r4, 14, $noreg, def $r0, def $r1 +# CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14, $noreg + +name: foo +tracksRegLiveness: true +body: | + bb.0: + liveins: $r2, $r4 + renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4) + dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg + renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4) + renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4) + tBcc %bb.1, 0, killed $cpsr + bb.1: + liveins: $r2, $r4 + renamable $r0 = tLDRi renamable $r2, 4, 14, $noreg :: (load 4) + dead renamable $r0, $cpsr = tADDi3 killed renamable $r0, 1, 14, $noreg + renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4) + renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4) + bb.2: + liveins: $r4 + TRAP |
