diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/trap.ll | 4 |
5 files changed, 14 insertions, 18 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index 1b874b97b27..8f1aaa1d893 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -74,19 +74,15 @@ public: TrapHandlerAbiHsa = 1 }; - enum TrapID { - TrapIDHardwareReserved = 0, - TrapIDHSADebugTrap = 1, - TrapIDLLVMTrap = 2, - TrapIDLLVMDebugTrap = 3, - TrapIDDebugBreakpoint = 7, - TrapIDDebugReserved8 = 8, - TrapIDDebugReservedFE = 0xfe, - TrapIDDebugReservedFF = 0xff + enum TrapCode { + TrapCodeBreakPoint = 0, + TrapCodeLLVMTrap = 1, + TrapCodeLLVMDebugTrap = 2, + TrapCodeHSADebugTrap = 3 }; enum TrapRegValues { - LLVMTrapHandlerRegValue = 1 + TrapCodeLLVMTrapRegValue = 1 }; protected: diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b266d16a92c..83ee856b4fe 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1804,7 +1804,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit); } else { switch (TrapType) { - case SISubtarget::TrapIDLLVMTrap: + case SISubtarget::TrapCodeLLVMTrap: BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM)); break; case SISubtarget::TrapCodeLLVMDebugTrap: { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index e832a0658d1..279745db467 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -632,9 +632,9 @@ def DSTOMOD { int NONE = 0; } -def TRAPID{ - int LLVM_TRAP = 2; - int LLVM_DEBUG_TRAP = 3; +def TRAPTYPE { + int LLVM_TRAP = 1; + int LLVM_DEBUG_TRAP = 2; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 5d147b24ec9..4bd759012a3 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -391,12 +391,12 @@ def SI_PC_ADD_REL_OFFSET : SPseudoInstSI < let Predicates = [isGCN] in { def : Pat< (trap), - (S_TRAP_PSEUDO TRAPID.LLVM_TRAP) + (S_TRAP_PSEUDO TRAPTYPE.LLVM_TRAP) >; def : Pat< (debugtrap), - (S_TRAP_PSEUDO TRAPID.LLVM_DEBUG_TRAP) + (S_TRAP_PSEUDO TRAPTYPE.LLVM_DEBUG_TRAP) >; def : Pat< diff --git a/llvm/test/CodeGen/AMDGPU/trap.ll b/llvm/test/CodeGen/AMDGPU/trap.ll index 15f055e8c2b..5c3e1ee0b3f 100644 --- a/llvm/test/CodeGen/AMDGPU/trap.ll +++ b/llvm/test/CodeGen/AMDGPU/trap.ll @@ -28,7 +28,7 @@ declare void @llvm.debugtrap() #0 ; GCN-LABEL: {{^}}hsa_trap: ; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] -; HSA-TRAP: s_trap 2 +; HSA-TRAP: s_trap 1 ; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information ; NO-HSA-TRAP: enable_trap_handler = 0 @@ -55,7 +55,7 @@ define void @hsa_trap() { ; GCN-LABEL: {{^}}hsa_debugtrap: ; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] -; HSA-TRAP: s_trap 3 +; HSA-TRAP: s_trap 2 ; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction ; NO-HSA-TRAP: enable_trap_handler = 0 |
