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-rw-r--r--llvm/lib/CodeGen/RegisterClassInfo.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index b0eeb81f583..5df32db4d99 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -49,9 +49,6 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
if (MF->getSubtarget().getRegisterInfo() != TRI) {
TRI = MF->getSubtarget().getRegisterInfo();
RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
- unsigned NumPSets = TRI->getNumRegPressureSets();
- PSetLimits.reset(new unsigned[NumPSets]);
- std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
Update = true;
}
@@ -80,8 +77,12 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
}
// Invalidate cached information from previous function.
- if (Update)
+ if (Update) {
+ unsigned NumPSets = TRI->getNumRegPressureSets();
+ PSetLimits.reset(new unsigned[NumPSets]);
+ std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
++Tag;
+ }
}
/// compute - Compute the preferred allocation order for RC with reserved
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