diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 25 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/machine-verifier.mir | 22 |
2 files changed, 47 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index eaa899576b7..3250ee5ef85 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -4570,6 +4570,31 @@ bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI, ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG"; return false; } + if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { + // Make sure we don't generate a lo-lo mov that isn't supported. + if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) && + !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) { + ErrInfo = "Non-flag-setting Thumb1 mov is v6-only"; + return false; + } + } + if (MI.getOpcode() == ARM::tPUSH || + MI.getOpcode() == ARM::tPOP || + MI.getOpcode() == ARM::tPOP_RET) { + for (int i = 2, e = MI.getNumOperands(); i < e; ++i) { + if (MI.getOperand(i).isImplicit() || + !MI.getOperand(i).isReg()) + continue; + unsigned Reg = MI.getOperand(i).getReg(); + if (Reg < ARM::R0 || Reg > ARM::R7) { + if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) && + !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) { + ErrInfo = "Unsupported register in Thumb1 push/pop"; + return false; + } + } + } + } return true; } diff --git a/llvm/test/CodeGen/ARM/machine-verifier.mir b/llvm/test/CodeGen/ARM/machine-verifier.mir new file mode 100644 index 00000000000..c5d678c38cf --- /dev/null +++ b/llvm/test/CodeGen/ARM/machine-verifier.mir @@ -0,0 +1,22 @@ +# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser runs the machine verifier after parsing. + +--- | + + define i32 @inc(i32 %a) { + entry: + ret i32 %a + } + +... +--- +name: inc +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK: *** Bad machine code: Unsupported register in Thumb1 push/pop *** + frame-setup tPUSH 14, $noreg, undef $r12, killed $lr, implicit-def $sp, implicit $sp + + ; CHECK: *** Bad machine code: Non-flag-setting Thumb1 mov is v6-only *** + $r2 = tMOVr killed $r6, 14, $noreg +... |
