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-rw-r--r--llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td34
-rw-r--r--llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td50
-rw-r--r--llvm/lib/Target/Mips/MipsDSPInstrInfo.td21
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt7
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt1
-rw-r--r--llvm/test/MC/Mips/micromips-dsp/valid.s7
-rw-r--r--llvm/test/MC/Mips/micromips-dspr2/valid.s1
7 files changed, 112 insertions, 9 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
index f231d3a5294..f24f80282b5 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
@@ -178,3 +178,37 @@ class POOL32A_1RAC_FMT<string instr_asm, bits<8> funct> : MMDSPInst<instr_asm> {
let Inst{13-6} = funct;
let Inst{5-0} = 0b111100;
}
+
+class POOL32A_1RMASK7_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
+ bits<5> rt;
+ bits<7> mask;
+
+ let Inst{31-26} = 0b000000;
+ let Inst{25-21} = rt;
+ let Inst{20-14} = mask;
+ let Inst{13-6} = op;
+ let Inst{5-0} = 0b111100;
+}
+
+class POOL32A_1RIMM10_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
+ bits<5> rd;
+ bits<10> imm;
+
+ let Inst{31-26} = 0;
+ let Inst{25-16} = imm;
+ let Inst{15-11} = rd;
+ let Inst{10} = 0;
+ let Inst{9-0} = op;
+}
+
+class POOL32A_1RIMM8_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
+ bits<5> rt;
+ bits<8> imm;
+
+ let Inst{31-26} = 0;
+ let Inst{25-21} = rt;
+ let Inst{20-13} = imm;
+ let Inst{12} = 0;
+ let Inst{11-6} = op;
+ let Inst{5-0} = 0b111100;
+}
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index 204a4ec60c5..9b4fb685318 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -141,6 +141,14 @@ class MFHI_MM_ENC : POOL32A_1RAC_FMT<"mfhi", 0b00000001>;
class MFLO_MM_ENC : POOL32A_1RAC_FMT<"mflo", 0b01000001>;
class MTHI_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b10000001>;
class MTLO_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b11000001>;
+class PREPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"prepend", 0b1001010101>;
+class RADDU_W_QB_MM_ENC : POOL32A_2R_FMT<"raddu.w.qb", 0b1111000100>;
+class RDDSP_MM_ENC : POOL32A_1RMASK7_FMT<"rddsp", 0b00011001>;
+class REPL_PH_MM_ENC : POOL32A_1RIMM10_FMT<"repl.ph", 0b0000111101>;
+class REPL_QB_MM_ENC : POOL32A_1RIMM8_FMT<"repl.qb", 0b010111>;
+class REPLV_PH_MM_ENC : POOL32A_2R_FMT<"replv.ph", 0b0000001100>;
+class REPLV_QB_MM_ENC : POOL32A_2R_FMT<"replv.qb", 0b0001001100>;
+class MTHLIP_MM_ENC : POOL32A_1RAC_FMT<"mthlip", 0b00001001>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
@@ -262,6 +270,7 @@ class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm");
InstrItinClass Itinerary = itin;
}
+
class EXTP_MM_DESC
: EXT_MM_1R_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
Uses<[DSPPos]>, Defs<[DSPEFI]>;
@@ -313,7 +322,38 @@ class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI,
class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO,
NoItinerary>;
-// Instruction defs.
+class RADDU_W_QB_MM_DESC {
+ dag OutOperandList = (outs GPR32Opnd:$rt);
+ dag InOperandList = (ins DSPROpnd:$rs);
+ string AsmString = !strconcat("raddu.w.qb", "\t$rt, $rs");
+ list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_raddu_w_qb DSPROpnd:$rs))];
+ InstrItinClass Itinerary = NoItinerary;
+ string BaseOpcode = "raddu.w.qb";
+}
+
+class RDDSP_MM_DESC {
+ dag OutOperandList = (outs GPR32Opnd:$rt);
+ dag InOperandList = (ins uimm16:$mask);
+ string AsmString = !strconcat("rddsp", "\t$rt, $mask");
+ list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp immZExt10:$mask))];
+ InstrItinClass Itinerary = NoItinerary;
+}
+
+class REPL_QB_MM_DESC {
+ dag OutOperandList = (outs DSPROpnd:$rt);
+ dag InOperandList = (ins uimm16:$imm);
+ string AsmString = !strconcat("repl.qb", "\t$rt, $imm");
+ list<dag> Pattern = [(set DSPROpnd:$rt, (int_mips_repl_qb immZExt8:$imm))];
+ InstrItinClass Itinerary = NoItinerary;
+}
+
+class REPLV_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
+ NoItinerary, DSPROpnd,
+ GPR32Opnd>;
+class REPLV_QB_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
+ NoItinerary, DSPROpnd,
+ GPR32Opnd>;
+
// microMIPS DSP Rev 1
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC;
@@ -404,6 +444,13 @@ def MFHI_DSP_MM : DspMMRel, MFHI_MM_ENC, MFHI_MM_DESC;
def MFLO_DSP_MM : DspMMRel, MFLO_MM_ENC, MFLO_MM_DESC;
def MTHI_DSP_MM : DspMMRel, MTHI_MM_ENC, MTHI_DESC;
def MTLO_DSP_MM : DspMMRel, MTLO_MM_ENC, MTLO_DESC;
+def RADDU_W_QB_MM : DspMMRel, RADDU_W_QB_MM_ENC, RADDU_W_QB_MM_DESC;
+def RDDSP_MM : DspMMRel, RDDSP_MM_ENC, RDDSP_MM_DESC;
+def REPL_PH_MM : DspMMRel, REPL_PH_MM_ENC, REPL_PH_DESC;
+def REPL_QB_MM : DspMMRel, REPL_QB_MM_ENC, REPL_QB_MM_DESC;
+def REPLV_PH_MM : DspMMRel, REPLV_PH_MM_ENC, REPLV_PH_MM_DESC;
+def REPLV_QB_MM : DspMMRel, REPLV_QB_MM_ENC, REPLV_QB_MM_DESC;
+def MTHLIP_MM : DspMMRel, MTHLIP_MM_ENC, MTHLIP_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;
@@ -454,3 +501,4 @@ def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC,
PRECR_SRA_PH_W_DESC, ISA_DSPR2;
def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC,
PRECR_SRA_R_PH_W_DESC, ISA_DSPR2;
+def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2;
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
index e8cfbcf572d..f696a38ac0f 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -275,6 +275,7 @@ class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
InstrItinClass Itinerary = itin;
+ string BaseOpcode = instr_asm;
}
class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -328,6 +329,7 @@ class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
InstrItinClass Itinerary = itin;
+ string BaseOpcode = instr_asm;
}
class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -383,6 +385,7 @@ class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
(OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
+ string BaseOpcode = instr_asm;
}
class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -428,6 +431,7 @@ class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
(OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
string Constraints = "$acin = $ac";
+ string BaseOpcode = instr_asm;
}
class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -437,6 +441,7 @@ class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
InstrItinClass Itinerary = itin;
+ string BaseOpcode = instr_asm;
}
class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -1107,7 +1112,7 @@ def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
def MODSUB : MODSUB_ENC, MODSUB_DESC;
-def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
+def RADDU_W_QB : DspMMRel, RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : DspMMRel, PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
@@ -1179,10 +1184,10 @@ def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
def BITREV : BITREV_ENC, BITREV_DESC;
def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
-def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
-def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
-def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
-def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
+def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
+def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
+def REPLV_QB : DspMMRel, REPLV_QB_ENC, REPLV_QB_DESC;
+def REPLV_PH : DspMMRel, REPLV_PH_ENC, REPLV_PH_DESC;
def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
def LWX : DspMMRel, LWX_ENC, LWX_DESC;
@@ -1204,8 +1209,8 @@ def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
def SHILO : SHILO_ENC, SHILO_DESC;
def SHILOV : SHILOV_ENC, SHILOV_DESC;
-def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
-def RDDSP : RDDSP_ENC, RDDSP_DESC;
+def MTHLIP : DspMMRel, MTHLIP_ENC, MTHLIP_DESC;
+def RDDSP : DspMMRel, RDDSP_ENC, RDDSP_DESC;
def WRDSP : WRDSP_ENC, WRDSP_DESC;
// MIPS DSP Rev 2
@@ -1256,7 +1261,7 @@ def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC;
def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC;
def APPEND : APPEND_ENC, APPEND_DESC;
def BALIGN : BALIGN_ENC, BALIGN_DESC;
-def PREPEND : PREPEND_ENC, PREPEND_DESC;
+def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC;
}
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
index ceba6a9823b..7fef4e2d08c 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
@@ -87,3 +87,10 @@
0x00 0x01 0x50 0x7c # CHECK: mflo $1, $ac1
0x00 0x01 0x60 0x7c # CHECK: mthi $1, $ac1
0x00 0x01 0x70 0x7c # CHECK: mtlo $1, $ac1
+0x00 0x22 0xf1 0x3c # CHECK: raddu.w.qb $1, $2
+0x00 0x20 0x86 0x7c # CHECK: rddsp $1, 2
+0x02 0x00 0x08 0x3d # CHECK: repl.ph $1, 512
+0x00 0x30 0x05 0xfc # CHECK: repl.qb $1, 128
+0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2
+0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2
+0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
index 8049e0e3174..096b5bda4a3 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
@@ -115,3 +115,4 @@
0x00 0x62 0x08 0x95 # CHECK: muleu_s.ph.qbl $1, $2, $3
0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3
+0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3
diff --git a/llvm/test/MC/Mips/micromips-dsp/valid.s b/llvm/test/MC/Mips/micromips-dsp/valid.s
index f2eae8f6cae..85e3cd6f4b9 100644
--- a/llvm/test/MC/Mips/micromips-dsp/valid.s
+++ b/llvm/test/MC/Mips/micromips-dsp/valid.s
@@ -88,3 +88,10 @@
mflo $1, $ac1 # CHECK: mflo $1, $ac1 # encoding: [0x00,0x01,0x50,0x7c]
mthi $1, $ac1 # CHECK: mthi $1, $ac1 # encoding: [0x00,0x01,0x60,0x7c]
mtlo $1, $ac1 # CHECK: mtlo $1, $ac1 # encoding: [0x00,0x01,0x70,0x7c]
+ raddu.w.qb $1, $2 # CHECK: raddu.w.qb $1, $2 # encoding: [0x00,0x22,0xf1,0x3c]
+ rddsp $1, 2 # CHECK: rddsp $1, 2 # encoding: [0x00,0x20,0x86,0x7c]
+ repl.ph $1, 512 # CHECK: repl.ph $1, 512 # encoding: [0x02,0x00,0x08,0x3d]
+ repl.qb $1, 128 # CHECK: repl.qb $1, 128 # encoding: [0x00,0x30,0x05,0xfc]
+ replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x00,0x22,0x03,0x3c]
+ replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x00,0x22,0x13,0x3c]
+ mthlip $1, $ac2 # CHECK: mthlip $1, $ac2 # encoding: [0x00,0x01,0x82,0x7c]
diff --git a/llvm/test/MC/Mips/micromips-dspr2/valid.s b/llvm/test/MC/Mips/micromips-dspr2/valid.s
index 3035ae5ba81..b236aea152a 100644
--- a/llvm/test/MC/Mips/micromips-dspr2/valid.s
+++ b/llvm/test/MC/Mips/micromips-dspr2/valid.s
@@ -116,3 +116,4 @@
muleu_s.ph.qbl $1, $2, $3 # CHECK: muleu_s.ph.qbl $1, $2, $3 # encoding: [0x00,0x62,0x08,0x95]
muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5]
mulq_rs.ph $1, $2, $3 # CHECK: mulq_rs.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x15]
+ prepend $1, $2, 3 # CHECK: prepend $1, $2, 3 # encoding: [0x00,0x22,0x1a,0x55]
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